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原创 HDLBITS: writing testbenches

You are provided a module with the following declaration:module dut ( input clk ) ;Write a testbench that creates one instance of module dut (with any instance name), and create a clock signal to drive the module's clkinput. The clock has a period of

2022-03-01 20:12:59 613

原创 Bulid a circuits from simulation waveform

This is a combinational circuit. Read the simulation waveforms to determine what the circuit does, then implement it.module top_module ( input a, input b, output q );// assign q = a&b; // Fix meendmoduleThis is a combina.

2022-02-28 14:56:14 480

原创 Finding bugs in code

This 8-bit wide 2-to-1 multiplexer doesn't work. Fix the bug(s).module top_module ( input sel, input [7:0] a, input [7:0] b, output out ); assign out = (~sel & a) | (sel & b);endmodule从上面的代码中我们可以看到，输出的out信号位宽不对，其次多路选择的表

2022-02-26 16:31:43 239

原创 Building larger circuit

Build a counter that counts from 0 to 999, inclusive, with a period of 1000 cycles. The reset input is synchronous, and should reset the counter to 0.module top_module ( input clk, input reset, output [9:0] q); always @(posedge clk) be

2022-02-23 14:30:35 148

原创 Finite State Machines

This is a Moore state machine with two states, one input, and one output. Implement this state machine. Notice that the reset state is B.This exercise is the same asfsm1s, but using asynchronous reset.

2022-02-13 14:57:33 503

原创 Sequential Logic-more circuits(feel free to look)

At each time step, the next state of each cell is the XOR of the cell's two current neighbours. A more verbose way of expressing this rule is the following table, where a cell's next state is a function of itself and its two neighbours:Left Center

2022-02-12 14:50:43 61

原创 Sequential Logic-Counters

Build a 4-bit binary counter that counts from 0 through 15, inclusive, with a period of 16. The reset input is synchronous, and should reset the counter to 0.module top_module ( input clk, input reset, // Synchronous active-high reset

2022-02-11 13:54:23 233

原创 Sequential logic-shift registers

构建一个4bit的移位寄存器(右移)，含异步复位、同步加载和使能areset：让寄存器复位为0 load：加载4bit数据到移位寄存器中，不移位 ena：使能右移 q：移位寄存器中的内容 module top_module( input clk, input areset, // async active-high reset to zero input load, input ena, input [3:0] data, output r

2022-01-26 15:05:37 363

原创 Sequential Logic-Latchs and Flip-Flops

D触发器：module top_module ( input clk, // Clocks are used in sequential circuits input d, output reg q );// always @(posedge clk) begin q<=d; end // Use a clocked always block // copy d to q at every positive

2022-01-25 14:26:09 276

原创组合逻辑电路-karnaugh map to circuit卡洛图

Implement the circuit described by the Karnaugh map below.module top_module( input a, input b, input c, output out ); assign out = (a | b | c);endmoduleImplement the circuit described by the Karnaugh map below.module .

2022-01-04 17:03:05 652

原创组合逻辑电路-arithmetic circuits

Create a half adder. A half adder adds two bits (with no carry-in) and produces a sum and carry-out.module top_module( input a, b, output cout, sum ); assign sum=a^b; assign cout=a&b;//{cout,sum}=a+b;endmoduleCreate a full add

2022-01-03 16:56:58 654

原创组合逻辑电路-multiplexer多路复用器

Create a one-bit wide, 2-to-1 multiplexer. When sel=0, choose a. When sel=1, choose b.module top_module( input a, b, sel, output out ); assign out = sel?b:a;endmoduleCreate a 100-bit wide, 2-to-1 multiplexer. When sel=0, choose a. When se

2022-01-03 15:32:44 1691

原创组合逻辑电路-basic gates

wire：Implement the following circuit:module top_module ( input in, output out);assign out=in;endmodulegnd：Implement the following circuit:module top_module ( output out); assign out=1'b0;endmoduleNOR:Implement the fol

2021-12-31 16:39:29 400

原创 verilog基础others

Conditional：条件运算符Verilog has a ternary conditional operator (?: ) much like C:(condition? if_true: if_false)This can be used to choose one of two values based on condition (a mux!) on one line, without using an if-then inside a combinational al...

2021-12-30 16:51:34 480

原创 verilog基础过程化

Alwaysblock1：Since digital circuits are composed of logic gates connected with wires, any circuit can be expressed as some combination of modules and assign statements. However, sometimes this is not the most convenient way to describe the circuit. Proce

2021-12-29 16:36:18 559

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