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原创 Allegro Design Extents最大值

这两天做了一个封装设计，发现Design Extents最大只能设置为：LeftX:-100000.0000 Width:200000.0000 LowerY:-100000.0000 Height:200000.0000. 单位是Microns.由于画布尺寸太小，没法正常生成drill table等fab文件。试了各种方式慢慢改大尺寸，都不行，最大只能设置到上述尺寸。后来发现是Accuracy定为了4. 把Accuracy改为3，即可再次改大画布尺寸了。...

2021-04-22 09:34:45 1313

原创 cadence17.2破解后安装HOTFIX的方法

cadence 17.2破解安装后，如果需要安装hotfix，则需要再次破解。查了一下网上只有16.6的相关教程，并无17.2的教程。所以把自己摸索的方案提供给大家：1. 首先把SPB_17.2文件夹命名为SPB_17.2_old(反正跟SPB_17.2不一样就行了，除此之外我又复制了整个SPB_17.2_old文件夹重命名为SPB_17.2_bak作为万一破解不成功的备份）2. 在Cadence目录里建一个空的文件夹SPB_17.2, 并把SPB_17.2_old的compnts.dat拷贝到空

2021-01-13 14:25:45 4584

IGXLHelp_3_60_10_P3.zip

Teradyne J750HD IGXL 3.60.10的帮助文件，chm格式，免安装。包含机台、板卡、软件介绍，编程方法，硬件设计方法

2021-04-22

Xilinx_ug583_PCB Guidelines for QDRII+SRAM.pdf

Xilinx的Guideline, 第2章详细介绍了“DDR3, DDR4, RLDRAM 3, QDR II+, QDR-IV, andLPDDR3 Memories”的PCB走线规则。可适用大部分ddr PCB设计。

2021-04-22

UltraFLEX_9.10.00.zip

ultra Flex 9.10.00 help 文件，chm格式。 This section provides views of IG-XL Help that can let you quickly focus on topics that are of particular interest to you based on your instrument configuration and testing needs. The following views are available: • Views by Instrument: The documentation that is available for each instrument. • Views by Device: For device types that are commonly tested with the UltraFLEX test system, the Test Technique Notes (TTNs) and Application Support Bulletins (ASBs) that can help in testing the device type. Note that you can also use the Search tab to find all instances of a particular term, concept, or other words and phrases. For more information on performing searches and filtering the results, see Using Search.

2020-03-25

Signal and Power Integrity - Si - Eric Bogatin.pdf

This third edition of Signal and Power Integrity—Simplified has one significant new addition over the previous edition: questions and problems at the end of each chapter to test and reinforce your understanding.

2019-06-26

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