sinat_27064525的博客

原创 Async FIFO

why gray code?in binary code :      FIFO address  从 010  变到  001 时由于亚稳态 ， 010 可能变成 011 或者 000 或者 010 或者 001 当变成 010 或者 001 时FIFO 空满的逻辑判断不会出错，而变成 011 或者 000 时FIFO 的逻辑判断会出错，这是不可取的。而用gray code, 相...

原创 verilog中reg类型的 output 真的就是 register 吗？

当 reg 类型 output 只在 combinational block里，则 output 其实是“wire型”，只有当output在sequencial block里才是真的register.

转载 cache VS buffer

Cache vs BufferBoth cache and buffer are temporary storage areas but they differ in many ways. The buffer is mainly found in ram and acts as an area where the CPU can store data temporarily, for examp...

转载 cache buffer SRAM DRAM

They are all memory - devices that remember information. They are really more descriptive terms, and there’s a lot of overlap between them.Main memory - memory that makes up most of the memory capacit...

转载 modelsim

转载 [Debug]modelsim simulation error,vsim:3053