scsi000的专栏

switch(genSensorMode) { default: case WDR_MODE_NONE: pstAeSnsDft->u32LinesPer500ms = gu32FullLinesStd*30/2; pstAeSnsDft->au8HistThresh[0] = 0xd; pstAeSnsDft->au8HistThresh[1] = 0x28; pstAeSnsDft->au8HistThresh[2] = 0x60; pstAeSnsDft->au8HistThresh[3] = 0x80; pstAeSnsDft->u32MaxAgain = 62564; pstAeSnsDft->u32MinAgain = 1024; pstAeSnsDft->u32MaxAgainTarget = pstAeSnsDft->u32MaxAgain; pstAeSnsDft->u32MinAgainTarget = pstAeSnsDft->u32MinAgain; pstAeSnsDft->u32MaxDgain = 4096; pstAeSnsDft->u32MinDgain = 1024; pstAeSnsDft->u32MaxDgainTarget = pstAeSnsDft->u32MaxDgain; pstAeSnsDft->u32MinDgainTarget = pstAeSnsDft->u32MinDgain; pstAeSnsDft->u8AeCompensation = 0x38; pstAeSnsDft->u32InitExposure = 76151; pstAeSnsDft->u32MaxIntTime = gu32FullLinesStd - 2; pstAeSnsDft->u32MinIntTime = 1; pstAeSnsDft->u32MaxIntTimeTarget = 65535; pstAeSnsDft->u32MinIntTimeTarget = 1; break; case WDR_MODE_2To1_LINE: pstAeSnsDft->u32LinesPer500ms = gu32FullLinesStd*25/2; pstAeSnsDft->au8HistThresh[0] = 0xC; pstAeSnsDft->au8HistThresh[1] = 0x18; pstAeSnsDft->au8HistThresh[2] = 0x60; pstAeSnsDft->au8HistThresh[3] = 0x80; pstAeSnsDft->u32MaxIntTime = gu32FullLinesStd - 2; pstAeSnsDft->u32MinIntTime = 2; pstAeSnsDft->u32MaxIntTimeTarget = 65535; pstAeSnsDft->u32MinIntTimeTarget = pstAeSnsDft->u32MinIntTime; pstAeSnsDft->u32MaxAgain = 62564; pstAeSnsDft->u32MinAgain = 1024; pstAeSnsDft->u32MaxAgainTarget = 62

The detailed information of NAD LGA is shown as following:模块详 细信息如下：  模块形态 → 单面 LGA  尺寸→ 52mm*52mm  电路板厚度 → 1.2mm  管脚大小→ 1.2mm  管脚数量→ 330  管脚距离→ 2.0 mm

STM8L15x Standard Peripherals Library_ Peripheral’s examples,ADC - AES - CLK - COMP - DAC - DMA - EXTI - FLASH - GPIO - I2C - ITC - IWDG - LCD - PWR - RTC - SPI - TIM - USART - WWDG

char syspath[255]; char sysport[64]; int count; char *pchar = NULL; int fd = 0; memset(idVendor, 0x00, 5); memset(idProduct, 0x00, 5); memset(bNumInterfaces, 0x00, 5); snprintf(sysport, sizeof(sysport), "/sys/class/tty/%s", &ttyport[strlen("/dev/")]); count = readlink(sysport, syspath, sizeof(syspath) - 1); if (count ../../devices/soc0/soc/2100000.aips-bus/2184200.usb/ci_hdrc.1/usb1/1-1/1-1:1.0/ttyUSB0/tty/ttyUSB0 pchar = strstr(syspath, ":1.0/tty"); //MDM if (pchar == NULL) { pchar = strstr(syspath, ":1.2/tty"); //ASR g_is_asr_chip = (pchar != NULL); } if (pchar == NULL) { qlog_dbg("%s is not a usb-to-serial device?\n", ttyport); return; } *pchar = '\0'; while (*pchar != '/') pchar--; strcpy(sysport, pchar + 1); snprintf(syspath, sizeof(syspath), "/sys/bus/usb/devices/%s/idVendor", sysport); fd = open(syspath, O_RDONLY); if (fd <= 0) { qlog_dbg("Fail to open %s, errno: %d (%s)\n", syspath, errno, strerror(errno)); return; } read(fd, idVendor, 4); close(fd);

FEATURES • High performance multi-bit delta-sigma audio ADC • 102 dB signal to noise ratio • -85 dB THD+N • 24-bit, 8 to 200 kHz sampling frequency • I 2 S/PCM master or slave serial data port • Support TDM • 256/384Fs, USB 12/24 MHz and other non standard audio system clocks • Low power standby mode

Product Description The PI3HDX511D is a small size DisplayPort dual mode Level Shifter and HDMI1.4b redriver packaged into 2.5x4.5mm size QFN with 48-bpp Deep Color support. This small QFN package with low power consumption is suitable to solve the ultra mobile devices, extremely tight design space limitations. PI3HDX511D has small stand-by current consumption less than 1mA to extend battery hours. In addition of small package advantage, it also support smart power states managements. Automatic squelch function can disable outputs signals when no input signal presents with Hot plug detection. Also ESD/EOS 8kV protection meets many set makers requirement. Features Low power small package size HDMI 1.4b compliant redriver with DisplayPort dual mode level shifter suitable for ultra-mobile application Operation up to 3.4 Gbps per lane (340MHz pixel clock) 4K Ultra HD, 3D Video formats (1080p, 1080i, 720p), 48-bit per pixel Deep Color support Low standby current <1mA with DDC passive switch mode Flexible 6 steps equalization control steps: 2.5, 5, 7.5 dB Pre-emphasis control 3 steps: 0, 1.5, 2.5 dB Automatic output squelch and HPD function for power saving states management at no input signal condition Convert low-swing DC or AC coupled differential input Integrated DDC level shifter 3.3V single power supply Integrated ESD protection on I/O pins, 8kV contact and 8kV HBM 30-pin QFN(ZL30) 2.5 x 4.5mm package Applications Ultra Mobile devices Notebook computers

Xilinx® 7 series FPGAs include four FPGA families that are all designed for lowest power to enable a common design to scale across families for optimal power, performance, and cost. The Spartan®-7 family is the lowest density with the lowest cost entry point into the 7 series portfolio. The Artix®-7 family is optimized for highest performance-per-watt and bandwidth-per-watt for cost-sensitive, high volume applications. The Kintex®-7 family is an innovative class of FPGAs optimized for the best price-performance. The Virtex®-7 family is optimized for highest system performance and capacity. This guide provides information on PCB design for 7 series FPGAs, with a focus on strategies for making design decisions at the PCB and interface level. This 7 series FPGAs PCB design user guide is part of an overall set of documentation on the 7 series FPGAs,

LT8618SX Low Power HDMI Transmitter Features  RGB Input  Support 24-bit RGB，YUV and BT656/BT601/BT1120 Input  Support both SDR and DDR Data Sampling  Programmable Rising/Falling Edge Clock Input  Support up to 148.5MHz DDR or 297MHz SDR Clock Input  Support both 1.8V and 3.3V Input Voltage Level  HDMI Transmitter  Compliant with HDMI1.4 and HDCP1.4  Resolution Up to 4K 30Hz  Programmable output swing and pre-emphasis  Fully hardware-controlled or optional software- controlled HDCP operations  Pre-programmed HDCP key sets or external EEPROM stored key sets  Integrated CEC controller  Integrated EDID shadow RAM and embedded EDID  5V tolerance DDC/HPD I/Os  Miscellaneous  1.8V and 3.3V Power Supply  Support 100KHz and 400KHz I2C slave  Support up to 8-channel Audio Input  Temperature Range: -40°C ~ +85°C  Pin compatible with SiI9030，ANX9030 and CAT6612  Packaged in LQFP80 12mm x 12mm and QFN64 9mm x 9mm Description The LT8618SX is Lontium’s low power version HDMI transmitter based on ClearEdgeTM technology. It supports the 24-bit color depth HDMI 1.4 (High Definition Multimedia Interface) specification. They are fully backwoard compatible with Lontium’s first generation HDMI transmitter LT8618EX, and also pin compatible with Silicon Image SiI9030 and Analogix ANX9030 transmitters. LT8618SX is a high performance, low power part that are specifically designed for HD-Digital cameras, HD-Digital Video Cameras, HD-PMP/MP4 Players, Cell phones, etc. The normal operation power is less than 100mA playing 24bit 1080P content, and the standby power is less than 2mA. Applications  DVD, BD  Car Video Recorder  PTV Box  HD Sources

Minimum Horizontal Blanking Specification Several cases define the minimum blanking time requirements. Vertical blanking times are normally multiples of the horizontal line times and do not place a constraint on performance. (HDMI requires at least two line times in each vertical blanking interval.) The minimum horizontal blanking time depends on the mode. An HSYNC or VSYNC edge can occur in any clock cycle except when active video data is being transmitted. When HDMI is active, this includes the two clocks of leading guard band for the active video data. Table 4.1. Minimum Horizontal Blanking Calculations

大华ip搜索工具是用于大华录像设备的IP搜索快速配置工具，使用configtool可以自动搜索大华摄像机ip地址，支持批量修改设备ip，当然也可以对设备进行系统升级，需要的就来下载吧。

海思SPI驱动源码，适用于Hi3531D,Hi3519A,Hi3559A等海思MPI芯片tatic void load_ssp_default_config(struct pl022 *pl022) { if (pl022->vendor->pl023) { writel(DEFAULT_SSP_REG_CR0_ST_PL023, SSP_CR0(pl022->virtbase)); writew(DEFAULT_SSP_REG_CR1_ST_PL023, SSP_CR1(pl022->virtbase)); } else if (pl022->vendor->extended_cr) { #ifdef CONFIG_ARCH_HISI_BVT struct amba_device *adev = pl022->adev; struct amba_driver *adrv = container_of(adev->dev.driver, struct amba_driver, drv); if (adev->periphid == adrv->id_t

500mA, Low Dropout, Low Noise, Ultra-Fast Linear Regulator

6787.ADV7842_Output_Pixel_Port_Mapping_Rev0-20091028 op_format_sel 00 01 02 06 0A 20 21 22 26 2A PIN NAME 8-BIT SDR ITU-656 MODE 0 10-BIT SDR ITU-656 MODE 0 12-BIT SDR ITU-656 MODE 0 12-BIT SDR ITU-656 MODE 1 12-BIT SDR ITU-656 MODE 2 8-BIT DDR ITU-656 MODE 0 10-BIT DDR ITU-656 MODE 0 12-BIT DDR ITU-656 MODE 0 12-BIT DDR ITU-656 MODE 1 12-BIT DDR ITU-656 MODE 2

STM32 GPIO模拟MIPI RFFE的代码实现， MIPI 规范简介， MIPIMASTER 读写时序波形

Three years after its founding, the Consortium for On-Board Optics (COBO) used OFC 2018 in San Diego last month as a stage on which to debut its long-awaited Release 1.0 specifications. The specifications cover three classes of onboard optical modules, backed by a pair of electrical interfaces. The optical modules will support transmission rates up to 800 Gbps. COBO expects the modules to meet a range of data center network requirements, including those that would require coherent transmission.

设置PCIE 的 去加重（de-emphasis）和前冲（preshoot）8GT/s 一致性眼图测试（Compliance Eye 8GT/s，Test 1.4） 该项测试的目的是验证被测系统的信号眼图的眼高和眼宽等是否满足CEM 规范的要求。 使用的码型为128B/130B 编码格式的一致性测试码型（compliance pattern）。由于Tx 发送端 波形有11 种preset，CEM 规范要求只要有一种 preset 码型（可选择一种最好的码型）通过 即可，可以任意选择preset 等于 1 或者7 或者 8 的码型进行测试，如果三种 preset 所对应的 码型都不能够通过，那么则需要继续测量余下的其它 preset 对应的码型，直到有通过为止， 否则需要将所有的 preset 对应的码型都测完以确定眼图测试是否通过。规范要求示波器一次 至少采集约1.5M 个UIs（比特位）进行测试，如果示波器采样率设置为 40GS/s，则需要采 集约8M 个数据点进行测试

RK3288 项目WiFi & BT 开发配置参考说明 1 RK3288 WIFI & BT 配置说明 1.1 RK3288 WiFi 内核配置 2 RK3288 WIFI & BT DTS 配置说明 2.1 RK3288 WiFi DTS 配置说明 2.2 RK3288 BT DTS 配置说明 3 RK3288 WIFI & BT 问题排查分析

IT6604 HDMI 1.4 3D Receiver Programming Guide Initial Progress 1. Set HPD (HDMI Connection Pin19) to low (if possible). 2. Reg06 = 0x00 to power on all modules. 3. Reg07[3:2] = ‘11’ to turn off the termination. 4. Reg05 = 0x81 5. Reg16 = 0x0F 6. Reg17 = 0x07 7. Reg18 = 0x07 8. Reg8C = 0x20 (5~8 is for initial interrupt mask setting) 9. Load the default value. 10. Reset the HDCP ROM. 11. Configure the HDCP repeater setting i) Receiver mode, reg73[7:4] = ‘0000’ ii) Repeater mode, reg73[7:4] = ‘1000’ 12. Delay about 500ms to make sure the HPD off enough. 13. Reg07[3:2] = ‘00’ 14. Set HPD to high (if possible). Initial Value List reg08 = 0xAE reg1D = 0x20 reg3B=0x40 reg68=0x03 reg6B=0x11 Reg6C=0x00 Reg93=0x43 Reg94=0x4F Reg95=0x87 Reg96=0x33

UDP 协议栈 IP。V1.3 - ARP timeout and ability to reset the ARP IP/MAC cache Migration notes: v1.2 to v1.3 - UDP_complete_nomac and IP_Complete_nomac have generics to specify clock rate and ARP timeout, and an additional control input. The generics can be left at their default values, the control input should have clear_cache set to '0'. V1.2 - Added handling for receipt of IP pkts with broadcast address ff.ff.ff.ff. Added is_broadcast flag to IP RX hdr. - Added ability to transmit IP pkts to broadcast address. Migration Notes: V1.1 to V1.2 - IP_RX_HDR has an additional output signal to indicate the IP pkt was received on the broadcast address. V1.1 - Added mac_tx_tfirst output to assist coupling to MAC layers that require a start of frame indication.

BC04参考设计指南, BC413159参考设计指南

Crane A10 定制化内容说明Crane A10 定制化内容说明.......................................................................................................2 1.1. Android Logo 及Boot Animation 修改................................................................ 2 1.2. 设备相关信息修改................................................................................................... 3 1.3. 预装APK ................................................................................................................... 4 1.4. 预设桌面方案.......................................................................................................... 5 1.5. 自定义按键.............................................................................................................. 5 1.6. Wifi 配置................................................................................................................. 7 1.7. LCD Panel 的修改.................................................................................................. 10 1.8. Touch Panel 的配置方法...................................................................................... 13 1.9. G-Sensor 的配置方法............................................................................................ 15 1.10. Camera 的配置方法.....

A10电路板应用手册. 第一章A10 开发板简介........................................................................................................................................ 5 1.1. A10 简介........................................................................................................................................................ 5 1.2. 开发板功能简介........................................................................................................................................... 5 1.3. 开发板配置................................................................................................................................................... 6 1.4. 开发板功能框图........................................................................................................................................... 7 1.5. 开发板电源框图........................................................................................................................................... 8 1.6. 典型应用....................................................................................................................................................... 9 1.7. 相关文档....................................................................................................................................................... 9 1.8. 联系方式....................................................................................................................................................... 9 第二章硬件资源 ................................................................................................................................................. 10 1.9. 外形尺寸图................................................................................................................................................. 10 1.10. 正面实物图............................................................................................................................................... 11 1.11. 背面实物图............................................................................................................................................... 12 1.12. 硬件资源................................................................................................................................................... 13 第三章硬件详述 ................................................................................................................................................. 14 1.13. CPU ...........................

蓝牙与2.4GRF对比蓝牙与2.4GRF对比,

功能实现: 在一个芯片与多个芯片或者设备需要通过串口进行通讯的时候, 可以采用串口扩展(一扩五)

Arria II 设计检查手册, 投板前必看

在Microsoft Visual C++下Inventor Coint3D 的安装与配置方法

VC 直接读写西门子 Simens PLC 数据 的DLL

本DLL可以实现对Excel文件的读写, 速度快, 可以支持一个Excel文件内的多个Sheet的读写. 但不支持公式,不支持色彩效果等,仅仅可以读写基本数据.

PCI EXPRESS 板卡设计指南: 1. Physical Interconnect Layout Design................................................ 5 1.1 Introduction ........................................................................................................ 5 1.2 Topology and Interconnect Overview .............................................................. 5 1.2.1 Card Interoperability ............................................................................................... 7 1.2.2 Bowtie Topology Considerations ............................................................................ 7 1.2.2.1 Lane Polarity Inversion.................................................................................................... 8 1.2.2.2 Lane Reversal and Width Negotiation ............................................................................. 8 1.3 Physical Layout Design Constraints............................................................... 11 1.3.1 PCB Stackup.......................................................................................................... 11 1.3.1.1 Desktop System Board and Add-in Card (4-layer) Stackup .......................................... 12 1.3.1.2 Server, Workstation and Mobile (6-layer, 8-layer and 10-layer) Stackups.................... 15 1.3.1.3 Add-in Card and Mobile (6-layer) Stackup ................................................................... 16 1.3.2 PCB Trace and Other Element Considerations ..................................................... 17 1.3.2.1 Differential Pair Width and Spacing Impacts ................................................................ 20 1.3.2.2 Differential Pair Length Restrictions and Budgets ........................................................ 23 1.3.2.3 Length Matching............................................................................................................ 24 1.3.2.4 Reference Planes............................................................................................................ 25 1.3.2.5 Breakout Area Specific Routing Guidelines .................................................................. 27 1.3.2.6 Edge Finger Design: Add-in Card ................................................................................. 29 1.3.2.7 Via Usage and Placement .............................................................................................. 30 1.3.2.8 Bends ............................................................................................................................. 32 1.3.2.9 Test Points and Probing ................................................................................................. 35 1.3.3 PCI Express Topologies ........................................................................................ 35 1.3.3.1 Interconnect Topologies for Two Components on the Baseboard ................................. 36 1.3.3.2 Interconnect Topologies for Baseboard with Add-in Card ............................................ 37 1.3.4 Passive Components and Connectors .................................................................... 38 1.3.4.1 AC Coupling Capacitors ................................................................................................ 38 1.3.4.2 Connectors ..................................................................................................................... 40 1.4 Summary........................................................................................................... 41

封装 FCPBGA 1143 工艺 28nm 低功耗工艺 典型功耗 30W(est.) 48x1G/48x2.5G/24x5G 下行，上行支持 10G/40G/25G/50G/100G 上联，并可 以使用 40G/50G/100G 等任意速率进行堆叠。 云时代和物联网高速发展，在接入交换节点，提出了更大表项，更低时延，更 灵活的流水线的需求。CTC7132 针对云时代的需求，深度优化流水线，打造了 TransWarp™第六代架构。 芯片特性  全面的二层特性  VLAN，MAC，LAG，广播风暴抑制等  VXLAN Bridge 大二层到边缘  802.1BR  DCB (PFC, ECN, ETS)优化 RDMA 流量  全面的三层特性  算法 ALPM 支持 IPv4 和 IPv6 双栈  线速的 NAT / NAPT / NAT-PT 转发  CAPWAP 隧道加解封装，分片重组，加解密  IPv4 和 IPv6 互转技术(6in4， 6to4，IVI 等)  全面的 MPLS 特性  LSP，L2VPN，L3VPN，L2VPN-L3VPN Gateway  Segment Routing  OAM/APS 特性  802.1ag/ Y.1731 以太网 OAM  G.8031/ G.8032 以太网业务保护  G.8113.1/ G.8113.2 MPLS-TP OAM  G.8131/ G.8132 MPLS-TP 业务保护  BFD/ OAM 检测自动保护切换  可视化特性  Buffer/Latency 监控  基于硬件的 NetFlow  ERSPAN (Ingress Timestamp and latency)  可编程特性  L2-L4 Programmable Edit  可编程隧道加解封装  安全和流量控制特性  支持 VLAN / MAC / Port / IP 进行 ACL 绑定  支持每个端口的 MACSec  支持基于 AES256 算法加密的 CloudSec  CPU 流量保护  时钟特性  IEEE 1588v2 和 Sync Ethernet

uint readtemp(void) { SCK=0; start(); //开始条件 SendByte(0x00); //发送从地址 00 SendByte(0x07); //发送命令 start(); //开始条件 SendByte(0x01); //读从地址 00 bit_out=0; tempL=ReadByte(); //读数据低字节 bit_out=0; tempH=ReadByte(); //读数据高字节 bit_out=1; err=ReadByte(); //读错误信息码 stop(); //停止条件 return(tempH*256+te

uint readtemp(void)

CMOS_CHECK_POINTER(pstAeSnsDft); IMX335_SENSOR_GET_CTX(ViPipe, pstSnsState); CMOS_CHECK_POINTER(pstSnsState); if (IMX335_5M_30FPS_12BIT_LINEAR_MODE == pstSnsState->u8ImgMode) { u32Fll = IMX335_VMAX_5M_30FPS_12BIT_LINEAR; U32MaxFps = 30; pstSnsState->u32FLStd = u32Fll*U32MaxFps/DIV_0_TO_1_FLOAT(gu32STimeFps); } else if (IMX335_5M_30FPS_10BIT_WDR_MODE == pstSnsState->u8ImgMode) { u32Fll = IMX335_VMAX_5M_30FPS_10BIT_WDR; U32MaxFps = 30; pstSnsState->u32FLStd = u32Fll*U32MaxFps/DIV_0_TO_1_FLOAT(gu32STimeFps); if (0 != (pstSnsState->u32FLStd % 4)) { pstSnsState->u32FLStd = pstSnsState->u32FLStd - (pstSnsState->u32FLStd % 4) + 4; //Because FSC value an integer multiple of 8 } pstSnsState->u32FLStd = pstSnsState->u32FLStd*2; } else if (IMX335_4M_30FPS_10BIT_WDR_MODE == pstSnsState->u8ImgMode) { u32Fll = IMX335_VMAX_4M_30FPS_10BIT_WDR; U32MaxFps = 30; pstSnsState->u32FLStd = u32Fll*U32MaxFps/DIV_0_TO_1_FLOAT(gu32STimeFps); if (0 != (pstSnsState->u32FLStd % 4)) { pstSnsState->u32FLStd = pstSnsState->u32FLStd - (pstSnsState->u32FLStd % 4) + 4; //Because FSC value an integer multiple of 8 } pstSnsState->u32FLStd = pstSnsState->u32FLStd*2; } else if (IMX335_4M_25FPS_10BIT_WDR_MODE == pstSnsState->u8ImgMode) { u32Fll = IMX335_VMAX_4M_25FPS_10BIT_WDR; U32MaxFps = 25; pstSnsState->u32FLStd = u32Fll*U32MaxFps/DIV_0_TO_1_FLOAT(gu32STimeFps); if (0 != (pstSnsState->u32FLStd % 4)) { pstSnsState->u32FLStd = pstSnsState->u32FLStd - (pstSnsState->u32FLStd % 4) + 4; //Because FSC value an integer multiple of 8 } pstSnsState->u32FLStd = pstSnsState->u32FLStd*2; } else { u32Fll = IMX335_VMAX_5M_30FPS_12BIT_LINEAR; U32MaxFps = 30; pstSnsState->u32FLStd = u32Fll*U32MaxFps/DIV_0_TO_1_FLOAT(gu32STimeFps); } //pstSnsState->u32FLStd = u32Fll;

CMOS_CHECK_POINTER(pstAeSnsDft); IMX335_SENSOR_GET_CTX(ViPipe, pstSnsState); CMOS_CHECK_POINTER(pstSnsState);

AAC格式的音频测试文件AAC，全称Advanced Audio Coding，是一种专为声音数据设计的文件压缩格式。与MP3不同，它采用了全新的算法进行编码，更加高效，具有更高的“性价比”。利用AAC格式，可使人感觉声音质量没有明显降低的前提下，更加小巧。苹果ipod、诺基亚手机支持AAC格式的音频文件。相较于mp3，AAC格式的音质更佳，文件更小。AAC属于有损压缩的格式，与时下流行的APE、FLAC等无损格式相比音质存在“本质上”的差距。加之，传输速度更快的USB3.0和16G以上大容量MP3正在加速普及，也使得AAC头上“小巧”的光环不复存在。