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TIA-EIA-568-B.2

qsgmii

JTAG_DESIGN

CAT-5

IEEE Draft P802.1s/D8

Supplement to Media Access Control (MAC) Bridges: GARP Proprietary Attribute Registration Protocol (GPRP)

Draft Standard P802.1Q/D7 IEEE Standards for Local and Metropolitan Area Networks: Virtual Bridged Local Area Networks

P802.1p Standard for Local and Metropolitan Area Networks — Supplement to Media Access Control (MAC) Bridges: Traffic Class Expediting and Dynamic Multicast Filtering

802.1d IEEE P802.1D/D15 November 24, 1997

3gpp标准 38101-1 38101-2 38101-3 .................................. 38905-f00 38912-f00 38913-f00

1. Introduction to M.2 Electro-Mechanical Specifications 1.1. Targeted Application 1.2. Specification References 2. Mechanical Specification 2.1. Overview 2.2. Card Type Naming Convention 2.3. Card Specifications 2.3.1. Card Form Factors Intended for Connectivity Socket 1 2.3.1.1. Type 2230 Specification 2.3.1.2. Type 1630 Specification 2.3.1.3. Type 3030 Specification 2.3.2. Card Form Factor Intended for WWAN Socket 2 2.3.2.1. Type 3042 Specification 2.3.3. Card Form Factor for SSD Socket 2

IEC61000-4-30-2008电磁兼容(EMC)试验和测量技术电能质量测量方法.pdf

GB9254-1998-传导骚扰.pdf

信息技术设备 安全 第1部分：通用要求GB 4943.1-2011.pdf

P2020 QorIQ Integrated Processor Design Checklist This document provides recommendations for new designs based on the P2020 QorIQ integrated processor. The P2020 combines dual e500v2 processor cores built on Power Architecture® technology with system logic required for networking, wireless infrastructure, and telecommunications applications. This document may also be useful in debugging newly-designed systems by highlighting those aspects of a design that merit special attention during initial system start-up. For updates to this document, see the website listed on the last page.

The following list provides an overview of the P2020 feature set: • Dual high-performance Power Architecture® e500 cores. • 36-bit physical addressing – Double-precision floating-point support – 32-Kbyte L1 instruction cache and 32-Kbyte L1 data cache for each core – 800-MHz to 1.2-GHz clock frequency • 512 Kbyte L2 cache with ECC. Also configurable as SRAM and stashing memory. • Three 10/100/1000 Mbps enhanced three-speed Ethernet controllers (eTSECs) – TCP/IP acceleration, quality of service, and classification capabilities – IEEE Std 1588™ support – Lossless flow control – R/G/MII, R/TBI, SGMII • High-speed interfaces supporting various multiplexing options: – Four SerDes to 3.125 GHz multiplexed across controllers – Three PCI Express interfaces – Two Serial RapidIO interfaces – Two SGMII interfaces • High-Speed USB controller (USB 2.0) – Host and device support – Enhanced host controller interface (EHCI) – ULPI interface to PHY • Enhanced secure digital host controller (SD/MMC) Enhanced Serial peripheral interface (eSPI) • Integrated security engine – Protocol support includes SNOW, ARC4, 3DES, AES, RSA/ECC, RNG, single-pass SSL/TLS, Kasumi – XOR acceleration • 64-bit DDR2/DDR3 SDRAM memory controller with ECC support

MPC8569E PowerQUICC III Integrated Processor Reference Manual The MPC8569E is a member of the PowerQUICC III family of devices that combine system-level support for industry-standard interfaces with processors built on Power Architecture technology. The device integrates an e500 core with system logic required for networking, telecommunications, and wireless infrastructure applications. The MPC8569E also incorporates the new QUICC Engine block, which provides termination, interworking, and switching among a wide range of communication protocols including ATM, Ethernet, HDLC, and POS. The QUICC Engine enhanced interworking eases the transition from ATM to IP-based systems and reduces investment costs. This chapter provides a high-level description of features and functionality of the device.

Altera’s new Cyclone® IV FPGA device family extends the Cyclone FPGA series leadership in providing the market’s lowest-cost, lowest-power FPGAs, now with a transceiver variant. Cyclone IV devices are targeted to high-volume, cost-sensitive applications, enabling system designers to meet increasing bandwidth requirements while lowering costs. Built on an optimized low-power process, the Cyclone IV device family offers the following two variants: This document provides an overview of features and functionality of the QorIQ chip communications processor. The chip combines dual Power Architecture e500v2 processor cores with system logic required for media, communications, and industrial applications. The chip offers an excellent combination of protocol and interface support including dual high-performance CPU cores, a DDR2/DDR3 memory controller, two enhanced threespeed Ethernet controllers with SGMII, RMII, and RGMII support, a secure digital interface, two USB 2.0 interfaces, audio/visual interfaces, and three PCI Express controllers. The device also supports the IEEE 1588TM precision time protocol for network synchronization over Ethernet. This manual is written from the perspective of the chip; the information also applies to the P1013, with the exception that the P1013 is a single-core device. This section describes the features of the device.

The Broadcom® BCM53118 is a highly integrated, cost-effective unmanaged-smart gigabit switch. The switch design is based on the field-proven, industryleading ROBO architecture. This device combines all the functions of a high-speed switch system including packet buffers, PHY transceivers, media access controllers (MACs), address management, portbased rate control, and a non-blocking switch fabric into a single 65 nm CMOS device. Designed to be fully compliant with the IEEE 802.3™ and IEEE 802.3x specifications, including the MAC-control PAUSE frame, the BCM53118 provides compatibility with all industry-standard Ethernet, Fast Ethernet, and Gigabit Ethernet (GbE) devices. The BCM53118 has a rich feature set suitable for not only standard GbE connectivity for desktop and laptop PCs, but also for next-generation gaming consoles, set-top boxes, networked DVD players, and home theater receivers. It is also specifically designed for next generation SOHO/SMB routers and gateways. The BCM53118 contains eight full-duplex 10/100/ 1000BASE-TX Ethernet transceivers. In addition, the BCM53118 has one GMII/RGMII/MII/RvMII/TMII interface for the CPU or a router chip, providing flexible 10/100/1000-Mbps connectivity. The BCM53118 provides 70+ on-chip MIB counters to collect receive and transmit statistics for each port. The BCM53118 is available in commercial temperature (C-Temp) rated packages. The commercial-grade BCM53118 is provided in a 256- pin eLQFP (28 mm × 28 mm) package.

The Broadcom® BCM56740+ family is a high-performance 480/640 Gbps network fabric with 18 integrated WarpCores. Each WarpCore has four integrated 10G SerDeses for native support of HiGig+™ and HiGig2™ at speeds of 10G, 12G, 13G, 15G, 16G, 20G, 21G, 25G, 30G, and 40G to support a wide range of configurations. The BCM56740+ is a purpose-built fabric chip designed to address performance and service requirements for data center and Metro Ethernet markets. The BCM56740+ architecture is optimized for maximum density with minimum power and board footprint and maintains software compatibility across the StrataXGS® product family to simplify customer designs and reduce customer time-to-market. As interfaces migrate from 1 GbE to 10 GbE and virtualization continues to increase link utilization, the demand for high-performance scalable chassis-based solutions will continue to grow. To obtain maximum scalability while minimizing oversubscription, the BCM56740 has integrated 10G SerDes with flexible port configuration options. With the BCM56740 fabric device, customers can build costeffective, high-performance, multichip chassis supporting over 5 Tbps of aggregate bandwidth. The features, integration, and low cost of the BCM56740 set a new standard in switch fabric design, and enable system vendors to build scalable and cost-effective next generation switching systems

This specification was developed by the SFF Committee prior to it becoming the SFF TA (Technology Affiliate) TWG (Technical Working Group) of SNIA (Storage Networking Industry Association).

This specification was developed by the SFF Committee prior to it becoming the SFF TA (Technology Affiliate) TWG (Technical Working Group) of SNIA (Storage Networking Industry Association).

This specification was developed by the SFF Committee prior to it becoming the SFF TA (Technology Affiliate) TWG (Technical Working Group) of SNIA (Storage Networking Industry Association).

SAS 标准3.0.0 Information technology - Serial Attached SCSI - 3 (SAS-3)

DDR2 SDRAM SPECIFICATION,JEDEC Standard,Package ballout & addressing,Functional description

Hardware and Layout Design Considerations for DDR3 SDRAM Memory Interfaces

ANSI\VITA 57.1_2008 /Revisions Under Consideration

This specification is a companion for the PCI Express Base Specification. Its primary focus is the implementation of an evolutionary strategy with the current PCI desktop/server mechanical and electrical specifications. The discussions are confined to ATX or ATX-based form factors. Other 5 form factors, such as Mini-PCI Express are covered in other separate specifications.

This introduction is not part of IEEE Std 802.3ap-2007, IEEE Standard for Information technology— Telecommunications and information exchange between systems—Local and metropolitan area networks— Specific requirements CSMA/CD Access Method and Physical Layer Specifications, Amendment 4: Ethernet Operation over Electrical Backplanes.

IS6806A 规格书 电气参数

EMMC标准 JESD84-B51

Open NAND Flash Interface Specification nand flash 标准

FMC 连接器规格书 连接器座子

FMC 接口标准ANSIVITA_57.1 The VITA 57.1 working group is considering the following changes to ANSI/VITA 57.1-2008 that would affect compliance and interoperability. NOTE: This information is provided for information only. While the working group is currently considering these changes, they may or may not be approved by the working group and may or may not become part of a revised standard. Contact VITA for more information. October 2008.

SGMII

RMII_spec

SGMIISpecification

SMII补充

smii

TIA_EIA_568_A