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界面清爽简洁 版本为：v0.17.1 开源MIT协议

vimplus一键安装包 官方说明：https://gitee.com/LionaDIE/vimplus/blob/master/README.md 本包特色：修改了官方包的GitHub地址（目前国内对GitHub的访问不友好），避免出现插件更新失败的问题。解决了安装后，出现插件加载失败的问题。 安装步骤：1.下载新版vim版本大于等于V8.2; 2.解压本程序包，一键安装。 安装建议：Ubuntu版本大于等于16.04.

本算法采用C语言开发，开发过程中，借鉴了mbedTLS的CCM算法思路。算法独立无依赖，原创全网首发；包含源文件sm4.c sm4.h ccm.c ccm.h和main.c作为demo程序。在linux环境下调试验证通过，算法独立，不依赖，移植性强。便于快速验证，开发项目！

源码包含国密算法SM4（ECB和CBC模式），独立模块，独立编译，亲测可用 压缩包包含3个文件：main.c sm4.c sm4.h 在linux环境下可直接编译，window环境下，添加到自己的工程中就可以使用。

桌面上的数字便笺 每个人都知道便笺，那些我们每天用来提醒我们的任务，错过的电话和其他重要的事情的黄色笔记？现在，您可以使用他们的数字版本与粘性！ 使用 Stickies，您可以用更环保、更高效的数字笔记取代传统的粘滞黄色音符，这些笔记被"固定"到桌面上。Stickies 笔记远不止小文本片段：您可以使用新的背景颜色和文本字体自定义它们的外观，将文件附加到它们，向它们添加警报等等。

适用于Windows 64-bit & 32-bit 该资源主要针对GitHub资源下载频繁失败的问题。亲测可用，测试环境VScode V1.44.0

GlobalPlatform是一家由支付和通信业的领先厂商、政府相关部门以及供应商社区共同建立的一个组织，并率先提出了一个跨行业的智能卡全局基础架构及其实现，其目标是为了减少隐藏在快速增长的跨行业、多应用的智能卡背后的障碍，使得发卡商在各种各样的卡片、终端和后台系统前，继续享有选择的自由。 为了充分挖掘智能卡的潜能，消费者需要能够有办法利用智能卡来完成各种功能。比如，利用手机上的智能卡来安全地连接到PC机上，进而通过互联网实现网上购物，或者利用智能卡来高效而便捷地完成其他各类功能等等。

本规范规定了: ——由接口设备至卡以及相反方向所发送的报文、命令和响应的内容; ——在复位应答期间卡所发送的历史字节的结构及内容; ——当处理交换用的行业间命令时，在接口处所看到的文件和数据的结构; ——访问卡内文件和数据的方法; ——定义访问卡内文件和数据的权利的安全体系结构; ——安全报文交换的方法; ——访问卡所处理算法的方法。本标准不描述这些算法。

本工具支持：（适用于嵌入式开发人员，APP数据处理人员，数据转换等） 1 数组增加0x； 2 数组去除0x标识； 3 字符串转16进制； 4 16进制转字符串； 5 大写转小写； 6 小写转大写； 7 字符串去空格；

该串口助手支持： 1 存储发送数据列表，保存数据后，可以设置发送规则。 2 支持完整的数据保存功能。 3 自动识别串口设备。 4 支持16进制/字符模式发送和接收

《CAN入门书》资源来自瑞萨官网，瑞萨在汽车电子领域的贡献大家有目共睹，所总结的资料详尽，准确。 该教程是国内大多工程师，研究CAN总线的必修资料。 文档条理清晰，深入浅出。

恒润在CAN总线设备上有较多研究，有着丰富的开发、应用经验，该教程能够帮助读者快速入门设备使用！ 快速了解在汽车领域的应用！

恒润在CAN总线设备上有较多研究，有着丰富的开发、应用经验，该教程能够帮助读者快速入门设备使用！

官方原版资料 RH850/F1L Group User’s Manual: Hardware Renesas microcontroller RH850 Family Section 1 Overview........................................................................................................ 63 1.1 RH850/F1L Products Features..................................................................................................... 63 1.1.1 RH850/F1L Functions......................................................................................................... 64 1.1.2 Internal Block Diagram ....................................................................................................... 68 Section 2 Pin Function................................................................................................... 74 2.1 Pin Connection Diagram............................................................................................................... 74 2.2 Pin Description.............................................................................................................................. 96 2.3 Ports and Pin Functions During and After Reset........................................................................ 101 2.4 Port State in Standby Mode........................................................................................................ 101 2.5 Recommended Connection of Unused Pins............................................................................... 102 2.6 RH850/F1L Port Features........................................................................................................... 103 2.6.1 Port Group........................................................................................................................ 103 2.6.2 Port Group Index n ........................................................................................................... 103 2.6.3 Register Base Address..................................................................................................... 103 2.7 Port Functions............................................................................................................................. 104 2.7.1 Functional Overview......................................................................................................... 104 2.7.2 Terms ............................................................................................................................... 105 2.7.2.1 JTAG Ports............................................................................................................ 105 2.7.3 Overview of Pin Functions................................................................................................ 106 2.7.4 Pin Data Input/Output....................................................................................................... 108 2.7.4.1 Output Data........................................................................................................... 108 2.7.4.2 Input Data.............................................................................................................. 108 2.7.4.3 Writing to the Pn Register ..................................................................................... 109 2.8 Port Type .................................................................................................................................... 110 2.9 Port Group Configuration Registers............................................................................................ 111 2.9.1 Overview........................................................................................................................... 111 2.9.2 Pin Function Configuration ............................................................................................... 114 2.9.2.1 PMCn / JPMC0 — Port Mode Control Register .................................................... 114 2.9.2.2 PMCSRn / JPMCSR0 — Port Mode Control Set/Reset Register.......................... 115 2.9.2.3 PIPCn — Port IP Control Register ........................................................................ 116 2.9.2.4 PMn / APMn / JPM0 — Port Mode Register ......................................................... 117 2.9.2.5 PMSRn / APMSRn / JPMSR0 — Port Mode Set/Reset Register.......................... 118 2.9.2.6 PIBCn / APIBCn / JPIBC0 / IPIBCn — Port Input Buffer Control Register............ 119 2.9.2.7 PFCn / JPFC0 — Port Function Control Register ................................................. 120 2.9.2.8 PFCEn — Port Function Control Expansion Register........................................... 121 2.9.2.9 PFCAEn — Port Function Control Additional Expansion Register........................ 122 2.9.3 Pin Data Input/Output....................................................................................................... 124 2.9.3.1 PBDCn / APBDCn / JPBDC0 — Port Bidirection Control Register ....................... 124 2.9.3.2 PPRn / APPRn / JPPR0 / IPPR0 — Port Pin Read Register ................................ 125 2.9.3.3 Pn / APn / JP0 — Port Register ............................................................................ 126 2.9.3.4 PNOTn / APNOTn / JPNOT0 — Port NOT Register............................................. 127 2.9.3.5 PSRn / APSRn / JPSR0 — Port Set/Reset Register............................................. 128 2.9.4 Configuration of Electrical Characteristics Registers........................................................ 129 2.9.4.1 PUn / JPU0 — Pull-Up Option Register ................................................................ 129 2.9.4.2 PDn / JPD0 — Pull-Down Option Register............................................................ 130 Table of Contents2.9.4.3 PDSCn — Port Drive Strength Control Register ................................................... 131 2.9.4.4 PODCn / JPODC0 — Port Open Drain Control Register ...................................... 132 2.9.4.5 PISn — Port Input Buffer Selection Register......................................................... 133 2.9.5 Port Register Protection ................................................................................................... 133 2.9.6 Flowchart Example for Port Settings ................................................................................ 134 2.9.6.1 Batch Setting......................................................................................................... 134 2.9.6.2 Individual Settings ................................................................................................. 135 2.10 Port (General I/O) Function Overview ........................................................................................ 138 2.10.1 JTAG Port 0 (JP0) ............................................................................................................ 139 2.10.1.1 Alternative Function............................................................................................... 139 2.10.1.2 Control Registers................................................................................................... 140 2.10.2 Port 0 (P0) ........................................................................................................................ 141 2.10.2.1 Alternative Function............................................................................................... 141 2.10.2.2 Control Registers................................................................................................... 143 2.10.3 Port 1 (P1) ........................................................................................................................ 147 2.10.3.1 Alternative Function............................................................................................... 147 2.10.3.2 Control Registers................................................................................................... 148 2.10.4 Port 2 (P2) ........................................................................................................................ 149 2.10.4.1 Alternative Function............................................................................................... 149 2.10.4.2 Control Registers................................................................................................... 150 2.10.5 Port 8 (P8) ........................................................................................................................ 151 2.10.5.1 Alternative Function............................................................................................... 151 2.10.5.2 Control Registers................................................................................................... 152 2.10.6 Port 9 (P9) ........................................................................................................................ 154 2.10.6.1 Alternative Function............................................................................................... 154 2.10.6.2 Control Registers................................................................................................... 155 2.10.7 Port 10 (P10) .................................................................................................................... 157 2.10.7.1 Alternative Function............................................................................................... 157 2.10.7.2 Control Registers................................................................................................... 159 2.10.8 Port 11 (P11) .................................................................................................................... 162 2.10.8.1 Alternative Function............................................................................................... 162 2.10.8.2 Control Registers................................................................................................... 165 2.10.9 Port 12 (P12) .................................................................................................................... 167

官方原版资料 RH850 Family 32 User’s Manual: Software Renesas microcontroller RH850 Family CHAPTER 1 OVERVIEW ...............................................................................................................1 1.1 V850E3v5 Architecture Features ...........................................................................................1 1.1.1 Multi-processing environment .....................................................................................2 1.1.2 Virtual machines...........................................................................................................2 1.1.3 Hardware multithreading..............................................................................................2 1.2 V850E3v5 Architecture Class ................................................................................................3 1.3 Changes from the V850E2v3 Architecture ............................................................................4 CHAPTER 2 PROCESSOR MODEL ................................................................................................5 2.1 Resource Management ...........................................................................................................5 (1) 3-layer control system..................................................................................................6 (2) 2-layer control system..................................................................................................7 2.2 CPU Operating Modes............................................................................................................8 2.2.1 Definition of CPU operating modes.............................................................................9 (1) Native mode (NM).......................................................................................................9 (2) Virtual machine mode (VM) .......................................................................................9 (3) Supervisor mode (SV) .................................................................................................9 (4) User mode (UM)..........................................................................................................9 2.2.2 CPU operating mode transition .................................................................................... 10 (1) Change due to acknowledging an exception ...............................................................10 (2) Change due to a return instruction...............................................................................10 (3) Change due to a system register instruction................................................................10 2.2.3 CPU operating modes and privileges...........................................................................11 (1) Hypervisor privilege (HV privilege) ...........................................................................12 (2) Supervisor privilege (SV privilege).............................................................................12 (3) Coprocessor use permissions.......................................................................................12 (4) Operation when there is a privilege violation .............................................................13 2.3 Hardware Thread ....................................................................................................................14 2.3.1 Thread status.................................................................................................................14 (1) Enabled/disabled..........................................................................................................14 (2) Stopped/running...........................................................................................................14 2.3.2 Stopping a thread by executing the HALT instruction ................................................15 2.3.3 Pausing a thread by executing the SNOOZE instruction.............................................15 2.4 Instruction Execution..............................................................................................................16 2.5 Exceptions and Interrupts .......................................................................................................17 2.5.1 Types of exceptions......................................................................................................17 (1) Terminating exceptions ...............................................................................................17 (2) Resumable exceptions .................................................................................................17 (3) Pending exceptions ......................................................................................................17 2.5.2 Exception level ................................................................................................................18 2.6 Coprocessors..............................................................................................................................18 2.6.1 Coprocessor use permissions...........................................................................................18 2.6.2 Correspondences between coprocessor use permissions and coprocessors ...................19 2.6.3 Coprocessor unusable exceptions....................................................................................19 2.6.4 System registers...............................................................................................................19 2.7 Registers.....................................................................................................................................20 2.7.1 Program registers.............................................................................................................20 2.7.2 System registers...............................................................................................................20 2.7.3 Register updating.............................................................................................................22 (1) LDSR and STSR..........................................................................................................22 (2) LDTC and STTC .........................................................................................................25

本资料面向 LIN 总线初学者，对什么是 LIN， LIN 的特征，物理层、协议层及应用层相关规定进行说明。 本资料主要是针对 LIN2.1 讲解。 使用注意事项............................................................................................................................................. 1 1. LIN是什么? ......................................................................................................................................... 4 1.1 LIN子网(Cluster)与节点(Node) ............................................................................................................ 5 1.2 主/从机节点与主/从机任务.................................................................................................................. 7 2. LIN的特点 ............................................................................................................................................. 8 3. LIN协议层 ............................................................................................................................................. 9 3.1 帧的结构............................................................................................................................................. 9 3.1.1 同步间隔段(Break Field) ................................................................................................................... 9 3.1.2 同步段(Sync Byte Field) .................................................................................................................. 10 3.1.3 受保护ID段(Protected Identifier Field).............................................................................................. 11 3.1.4 数据段(Data Field)........................................................................................................................... 12 3.1.5 校验和段(Checksum Field) .............................................................................................................. 13

用于编辑【描述CAN的DBC文件】，随后借助硬件数据，即可实现应用层数据解析

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