wy27258745的博客

官网搬运，用于cp210x 修改 pid vid 序列号等参数，CP210xSetIDs是v3.0最新版

由于最新的QT9.11.2安装后没有带32位的库文件，自己编译了一个，耗时半天，已测试可以正常使用

自己项目上要做生产文件，bin比较麻烦要填地址所以写了个bin转mot的代码，刚写的代码还带着热气哦 //char*in bin文件路径 //char* out mot文件路径 //unsigned int addr bin文件偏移地址

LPC17 系列MCU数据手册 英文原版第二版 Rev. 2 — 12 August 2010

Cadence Virtuso Layout Editor 快捷键归纳

成功大学硕士论文 This thesis presents the development of 5.7 GHz CMOS RFICs for the IEEE 802.11a WLAN RF receiver and a 5.7 GHz two stage class-A CMOS PA in TSMC standard 0.18mm CMOS process. The CMOS RF receiver includes a differential LNA with gain control, an active double-balanced mixer, and an L-C tank CMOS VCO. The RF is from 5.725 to 5.825 GHz, the LO is from 5.265 to 5.325GHz and the IF is at 480 MHz. The LNA exhibits a gain of 11dB, noise figure of 4.2dB and input P1dB of –11dBm. The mixer exhibits a conversion gain of 11.06dB, noise figure of 12.8dB and input P1dB of –16.4dBm. The L-C tank CMOS VCO has an output frequency from 5099 to 5242MHz with -90.8dBc/Hz@100KHz phase noise. The VCO is used in a designed 5- GHz frequency synthesizer. The synthesizer with a spur below 58dBc has a settling time of 71.3ms for 20MHz step. The 5.7-GHz CMOS RF receiver (with the frequency synthesizer) exhibits a conversion gain of 19.1dB, noise figure of 6.6dB, input P1dB of – 30.8dBm. For the digital modulation measurement, a 5.744MHz 802.11a 18Mbps and 54Mbps OFDM signal are applied to the receiver. The measured EVM is about 2.57%(QPSK) and 1.96%(64QAM).

HSpice 0.35um CMOS 工艺库

电流镜是模拟CMOS集成电路中最基本的结构之一