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Working Draft Project American National Standard ,Project T10/2212-D, Revision 01, 23 April 2012,Information technology - Serial Attached SCSI - 3 (SAS-3). Specification.

ANSI_VITA 46.0-2007_American National Standard for VPX Baseline Standard

Enterprise_SSD_Form_Factor_SPEC_Version1_00 This specification defines the electrical and mechanical requirements for a PCI Express connection to the existing standard 2.5” and 3.5” disk drive form factors. This is intended for PCIe connections to SSDs (Solid State Drives) for the enterprise market of servers and storage systems. This provides a new PCIe form factor that is storage friendly, leveraging both the existing PCIe specification and the existing 2.5” and 3.5” drive mechanical specifications. This standard allows system designs that can support a flexible mix of new enterprise PCI Express drives, and existing SAS and SATA drives.

PCI Express M.2 specification-Revision 0.7, Version 1.0,November 27, 2012, The M.2M.2 form factor is used for Mobile Add-In cards. The M.2 is a natural transition from the Mini Card and Half-Mini Card to a smaller form factor in both size and volume. The M.2 is a family of form factors that will enable expansion, contraction, and higher integration of functions onto a single form factor module solution. The key target for M.2 is to be significantly smaller in the XYZ and overall volume of the Half-Mini Card used today in mobile platforms in preparation for the very thin computing platforms (for example; Notebook, Tablet/Slate platforms) that require a much smaller solution.

PCI工作小组(PCI-SIG)最近公布PCIe Base 3.0规格；PCIe 3.0架构的I/O技术，包括128bit/130bit的编码方案以及8GT/s的数据传输速率，互连带宽是PCIe 2.0规格的两倍。PCIe 3.0还维持与旧版PCIe架构的向下兼容，适用的拓朴形态包括服务器、工作站、桌面计算机、行动PC、嵌入式系统与各种外围设备。 PCI-SIG表示，以8GT/s的数据传输速率为基础，意味着PCIe 3.0架构产品带宽，可能达到单线(x1)配置每秒1GB，或是扩充到以16线(x16)配置、每秒32GB。该组织并指出，新版规格整合了众多通讯协议与软件层(software layers)的增强功能，涵盖数据重用提示(data reuse hints)、原子作业(atomic operation)、动态功率调整机制(dynamic power adjustment mechanism)、延迟容忍报告(latency tolerance reporting)、松散交易定序(loose transaction ordering)、I/O页面错误等等支持平台省电性、软件模块灵活性与架构可扩展性的延伸功能。

Verilog HDL A Guide to Digital Design and Synthesis, Second Edition

Up to a few years ago, the approaches taken to check whether a hardware component works as expected could be classied under one of two styles: hardware engineers in the industry would tend to exclusively use simulation to (empirically) test their circuits, whereas computer scientists would tend to advocate an approach based almost exclusively on formal verication. This thesis proposes a unied approach to hardware design in which both simulation and formal verication can co-exist. Relational Duration Calculus (an extension of Duration Calculus) is developed and used to dene the formal semantics of Verilog HDL (a standard industry hardware description language). Relational Duration Calculus is a temporal logic which can deal with certain issues raised by the behaviour of typical hardware description languages and which are hard to describe in a pure temporal logic. These semantics are then used to unify the simulation of Verilog programs, formal verication and the use of algebraic laws during the design stage. A simple operational semantics based on the simulation cycle is shown to be isomorphic to the denotational semantics. A number of laws which programs satisfy are also given, and can be used for the comparison of syntactically different programs. The thesis also presents a number of other results. The use of a temporal logic to specify the semantics of the language makes the development of programs which satisfy real-time properties relatively easy. This is shown in a case study. The fuzzy boundary in interpreting Verilog programs as either hardware or software is also exploited by developing a compilation procedure to translate programs into hardware. Hence, the two extreme interpretations of hardware description languages as software, with sequential composition as the topmost operator (as in simulation), and as hardware with parallel composition as the topmost operator are exposed. The results achieved are not limited to Verilog. The approach taken was carefully chosen so as to be applicable to other standard hardware description languages such as VHDL.

随着通信科技的不断提升，必然对PCB的要求也有了相应的提高，传统意义上PCB已受到严峻的挑战，以往PCB的最高要求open&short从目前来看已变成PCB的最基本要求，取而代之的是一些为保证客户设计意图的体现而在PCB上所体现的性能的要求。如阻抗控制等。 深南电路公司作为中国大陆最早为通信企业提供PCB的厂商，在1997年就对该课题进行研究和开发。 到目前为止有“阻抗”控制的PCB已广泛的应用于：SDH、GSM、CDMA、PC、大功率无绳电话、手机等同时也为国防科技提供了相当数量的PCB。

Advanced® 3.0 Release 2.0 PICMG® Base Specification

Verilog HDL是一种硬件描述语言，用于从算法级、门级到开关级的多种抽象设计层次的 数字系统建模。被建模的数字系统对象的复杂性可以介于简单的门和完整的电子数字系统之 间。数字系统能够按层次描述，并可在相同描述中显式地进行时序建模。