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转载 总线与数据的字节对齐

原文链接: http://blog.chinaunix.net/uid-22283027-id-3985411.html.首先要明白总线的概念数据总线(1) 是CPU与内存或其他器件之间的数据传送的通道。(2)数据总线的宽度决定了CPU和外界的数据传送速度。(3)每条传输线一次只能传输1位二进制数据。eg: 8根数据线一次可传送一个8位二进制数据(即一个字节)。(4)数据总线是数据线数...

2019-11-18 16:54:05 755 1

转载 Timing Path

原文链接: http://blog.chinaaet.com/heyuanpi/p/5100053503.Timing Path的概念从register clock/input port开始,经过一些combinational logic,终止在register data/output port,组合一下共有四种类型的path:in2reg,in2out,reg2reg,reg2out===...

2019-11-10 18:43:10 3280

TMS320F28004x Technical Reference Manual.pdf

TMS320F28004x Real-Time Microcontrollers Technical Reference Manual (Rev. D).pdf

2021-12-02

TMS320C6748 Fixed- and Floating-Point DSP datasheet (Rev. G).pdf

TMS320C6748 Fixed- and Floating-Point DSP datasheet (Rev. G).pdf

2021-12-02

MX25L25735F.pdf

3V 256M-BIT [x 1/x 2/x 4] CMOS MXSMIO (SERIAL MULTI I/O) FLASH MEMORY

2021-06-09

UVM平台搭建过程.pdf

UVM+VCS+Verdi 的 liunx 平台搭建过程和 Questa-sim+UVM 的 window 平台搭建。

2020-05-16

DB-SFD64KX32M64P4C-HE-LMC-100B-BC.pdf

The SFD64KX32M64P4C_HE_LMC is a CMOS page erase, double word( 32-bit) program Embedded Flash Memory which is partitioned into two memory blocks. One is the main memory block, the other is the information block .The main memory block is organized as a 65536 word by 32 bit. The information block is organized as a 512 word by 32 bit . The information block can be used for the storage of device information. The page erase operation erases all double words within a page. A page is composed of 4 adjacent rows for main memory block and 4 adjacent rows for information block .The split gate cell design and thick oxide tunneling injector attain better reliability and manufacturability compared with alternative approaches. The SFD64KX32M64P4C_HE_LMC erases and programs with a 1.8-volt only power supply

2019-11-29

嵌入式存储器内建自测试方法.pdf

嵌入式存储器内建自测试方法:1.存储器故障表现和故障模型;2.储器测试算法;3.入式存储器BIST的实现原理。

2019-11-24

sram_sp_hse_8kx8.pdf

Precise Optimization for TSMC’s Six-Layer Metal 0.18µm CL018G CMOS Process • High Density (area is 0.496mm2) • Fast Access Time (1.51ns at fast@0C process, 1.98V, 0˚C) • Fast Cycle Time (1.51ns at fast@0C process, 1.98V, 0˚C) • One Read/Write Port • Completely Static Operation • Near-Zero Hold Time (Data, Address, and Control Inputs) Memory Description The 8192X8 SRAM is a high-performance, synchronous single-port, 8192-word by 8-bit memory designed to take full advantage of TSMC’s six-layer met

2019-11-17

sram_sp_hse_8kx8.v

Verilog代码文件sram_sp_hse_8kx8.v,8kx8 Single-Port Ram,TSMC CL018G 180nm Process 4.655^um Bit Cell

2019-11-17

Discovery Visual Environment User Guide.pdf

VCS官方手册,使用指南,Discovery Visual Environment User Guide.pdf

2019-11-01

verilog RTL编码实践code.zip

03设计课 verilog RTL编码实践的对应code, 内含7个Lab和一个library。

2019-10-28

Questasim _10.1d_linux32安装包.txt

内含Questasim _10.1d_linux32安装包百度网盘链接,破解请参考网上教程,不需要在windows再安装一遍,可以把linux安装后的linux文件夹复制到windows,使用破解文件处理。对于linux,patch_dll.bat里面只有MentorKG.exe -patch最重要,mgls.dll不存在无所谓,环境变量在user目录的.bashrc中设置LM_LICENSE_FILE,如果已经存在LM_LICENSE_FILE,就再写一行,分号分隔什么的是windows里面的方法,linux没有用。

2019-10-28

系统芯片(SOC)验证方法与技术.rar

系统芯片(SOC)验证方法与技术,内含pdg文件,可以用超星阅读器打开。

2019-10-15

VCS_labs.rar

数字逻辑仿真工具实践VCS对应的实验代码,共有8个Lab。

2019-10-15

Advanced ASIC Chip Synthesis_Using Synopsys® Design Compiler™_second edition.pdf

Advanced ASIC Chip Synthesis_Using Synopsys® Design Compiler™_second edition

2019-10-09

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