weixin_42340005的博客

一种基于FPGA的UPP接口代码实现connect_debug_port u_ila_0/probe45 [get_nets [list tx2_lock]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe46] set_property port_width 1 [get_debug_ports u_ila_0/probe46] connect_debug_port u_ila_0/probe46 [get_nets [list tx3_lock]] set_property C_CLK_INPUT_FREQ_HZ 300000000 [get_debug_cores dbg_hub] set_property C_ENABLE_CLK_DIVIDER false [get_debug_cores dbg_hub] set_property C_USER_SCAN_CHAIN 1 [get_debug_cores dbg_hub] connect_debug_port dbg_hub/clk [get_nets sync_clk_out]

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