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阻赛与非阻赛中文Verilog_NBA.doc
在Verilog语言最难弄明白的结构中“非阻塞赋值”要算一个。甚至是一些很有经验的工程师也不完全明白“非阻塞赋值”在仿真器(符合IEEE标准的)里是怎样被设定执行的,以及什么时候该用“非阻塞赋值”。这篇文章将介绍怎样设定“非阻塞赋值”和“阻塞赋值”,给出了重要的使得编码可以被正确地综合的编码指导方针,和避免仿真竞争的编码风格细节。
2011-01-09
Verilog_coding_style_guidelines.pdf
The blocking assignment operator is an equal sign ("="). A blocking assignment gets its name
because a blocking assignment must evaluate the RHS arguments and complete the assignment
without interruption from any other Verilog statement. The assignment is said to "block" other
assignments until the current assignment has completed. The one exception is a blocking
assignment with timing delays
2009-06-11
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