quan123hhhh的博客

egin if clk'event and clk = '0' then datacon dataflag dataflag dataflag dataflag dataflag dataflag dataflag dataflag dataflag <= dataflag; end case; BDataOut <= dataflag; end if;

数字滤波器，能够通过，希望可以帮到各位 library work; use work.eight_bit_int.all; library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; entity firfilter is port(clk :in std_logic; x: in fbyte; y: out fbyte); end firfilter;