naclkcl9-CSDN博客

原创 VMM testbench diagram

如上图， vmm testbench的结构如下SYSCfg 包含了全局开关，这些开关控制了是否允许randomize，是否启用default值，是否允许error/delay injection， run_for_n_packets. REGCfg 包含了register要配置的初始值，memory的初始值CfgDUT 调用RAL的handler，根据REGCfg的值配置各

2010-02-26 16:53:00 2136

原创 VMM coding style -- recommended by synopsys AE

1. 定义一个系统级的config类，如 syscfg. 在类中集中了所有的控制变量（总开关），这些变量决定了是否允许randomize，error injection， delay injection，产生包的个数，等等这样可以有效的消除一些不必要的callback。一般callback只是用于将某段代码开放给后面的维护人员以便进行一些复杂的修改之用。 Callb

2010-02-25 09:55:00 2974 1

原创再谈VMM文件的组织形式

上次谈到的VMM的组织形式，VCS编译器不能很好的支持。根据synopsys的指导更新一下如何组织VMM testbench1. testcase 在 programe 语句块内 include vmm_sv 以及 tb_env.sv2. tb_env class 定义之外 include 所有的 vmm_data, vmm_xactor的扩展类，并且严格按照调用顺序。3. 所有的

2010-02-24 11:43:00 1685

原创 timescale problem in systemverilog

如果没有指定timescale，或者 timeunit 那么整个环境会用default的值，（VCS 好像是秒 s），如果你在code中使用了......#1ns;......对不起，这一纳秒的delay被完全忽略了。因为1ns小于timescale的精度, 所以被忽略为零。因此个人以为应该1）指定timescale2）尽量用不带单位的delay

2012-03-22 11:13:11 3002

转载 VMM VIP’s on multiple buses

A better approach is one that was described by Janick in the “Size Does Matter” blog of using `define. Let’s expand on this and see how it works for reusable VIPs. Well, the first thing that comes t

2012-03-16 10:15:02 2372

原创 VMM 中 factory 所用的 copy 和 allocate 方法的区别

在VMM1.1 以及之前，其factory机制的实现是通过以下两种方法实现的1） copy ：如下class xxx base_transaction factory; .... factory=new(); .... base_transaction tr; $cast(tr, factory.copy())endcl

2012-03-11 18:10:06 3171

转载养身

张进良讲中医奇术良好的生活习惯决定着一个人的健康指数，快乐的情绪是健康的源泉，健康就把握在自己手里！--张进良医生要求患者配合部分：药物不是万能的，树立良好的健康观念，才是你最终健康的唯一途径。早晨6：30分至7：00尽量起床：此时阳气正旺，适合轻微活动，漫步、打太极最好。激活人体的能量系统。（可以锻炼，但是不可出大汗为原则）。中午：12点前尽量不要卧床12

2012-03-10 17:40:34 5124

原创 DesignWare VIP 的 define 文件

用过DW VIP的童鞋们一定会感受到里面一堆define文件的痛苦，下面就粗略的谈谈和define相关的知识。1. VIP原代码中大量运用了ifdef ，即意味着如果外界定义了某宏则使用外界最终定义的宏，否则使用内部预定义的default值。这里支持redefine。2. 外界预定义的宏放在 include/verilog 目录下，主要如下： AhbMasterDefine

2012-03-06 15:14:43 3236

原创 multi stream scenario （vmm_ms_scenario）几点补充

1. vmm_ms_scenario 也可以利用factory 模式class cpu_rand_scenario extends vmm_ms_scenario; cpu_trans blueprint; `vmm_scenario_new(cpu_rand_scenario) function new()

2012-02-27 16:19:43 2633

原创 RAL来龙去脉补充

下面讲一下 vmm_ral_env 中的ral, 以及 vmm_ral_access类的介绍。先看一下vmm_ral_env的源代码：class vmm_ral_env extends `VMM_ENV; vmm_ral_access ral; extern function new(string name = "RAL-Based Verif Env");

2012-02-25 13:48:51 3651

原创 strings 提取 features

strings 是 Linux 命令，提取可执行文件中的字符串，你找到一个 Feature 名字，其他 Feature 名字就在附近，许多 .src 是这样生成的

2012-02-17 20:39:31 1717

转载 Datastream scoreboard iterators

Datastream scoreboard iterators are objects that know how to traverse and navigate theimplementation of the scoreboard. They provide high level methods for moving through thescoreboard and modifyi

2012-02-16 20:43:06 1881

转载 VMM Callbacks Versus TLM Analysis Ports

Question:Do I use VMM callbacks or TLM analysis ports to broadcast information from a transactor? Answer:After the OSCI TLM 2.0 features were added to VMM 1.2, it is possible to use anal

2012-02-14 18:30:44 2409

转载 MAM example

VMM application package offers capability to dynamically manage memory shared between multiple clients via Memory Allocation Manager (MAM). MAM helps to simulate HW memory usage patterns and guara

2012-02-12 20:43:12 3237

转载 memory allocation manager

UVM MAM (Memory Allocation Manager) manages the exclusive allocation of consecutive memory locations called regions. The regions can subsequently be accessed like little memories of their own, witho

2012-02-12 20:31:53 4470

原创 how does Interface Wrapper promote re use / ease of use of interface class

My question is how does it help / add value to have the virtual interface in a wrapper class and initialize / configure using vmm_opts related code ?In summary , how does Interface Wrapper promo

2012-02-09 00:11:33 1926

转载 How does VCS support parameterized virtual interface?

Answer:1. Following is an example of using a parameterized virtual interface with legal or illegal assignments which works as mentioned(in comments/LRM) in VCS:------------------

2012-02-09 00:01:51 2038

转载 Creating Configurable Environments with Hierarchical and Global Options (vmm_opts) in VMM

Verification environments need to accommodate changing specifications and at the same time cater to the requirements of different clusters and subsystems.vmm_opts provides the ability to provide a

2012-02-08 23:45:48 3000 1

原创 vmm_test初步研究

vmm_test 的实现机制 my_test 通常也称为wrapper class . 上图中红颜色的是静态object

2012-02-01 13:50:59 2648 1

转载 vmm debug problem

Here is a reference of compile script and filelist, the DVE tbug is ok, please have a try. //---------------------test.files----------------------------------------AxiMaster_rvm.pkgAhbSlave

2012-01-29 18:24:02 2695

转载 How to covert AHB BUS monitor VIP to AHB Master Port monitor

Below is an example on how to covert the AHB Bus monitor to a Port Monitor for Master: Step 1: in the TBTop, do as below(wire-connection): //***************************************************

2012-01-29 18:12:39 2692

转载 How to generate response for AHB Slave VIP

You can create a “ahbSlaveResponser.sv” that extends from vmm_xactor, and the responses are “transfer” level based, that is, if a burst read/write have 4 transfers, the Slave VIP will send 4 objects t

2012-01-29 18:03:59 2591

转载 how to generate AXI VIP built-in coverage

There is a built-in AXI VIP example that can show you how to generate AXI VIP built-in coverage, it also shows how user can define their own functional coverage groups.You can install the example wi

2012-01-29 17:56:50 2567

转载 AXI VIP 中定义自己的define文件

Normally, the interface file “axi_if.sv “ includes a” AxiPortDefines.inc” file , which has lots of `defines with default values, and may mismatch with your real design. `define DW_VIP_AXI_ADDR_POR

2012-01-29 17:54:10 1165

转载 AXI Slave VIP that control the delay between the AREADY and AVALID

There are two variables in AXI Slave VIP that control the delay between the AREADY and AVALID: MAX: dw_vip_axi_port_configuration :: m_nMaxDelay = 5000 MIN: m_nAvalidAreadyDelay = 0;

2012-01-29 17:45:15 1501

原创 assertions 使用问答

1. 如何防止在simulation结束仍然还未结束的assertion打印出消息？VCS supports disabling the SVA unfinished message reporting at the end of simulation, please do as follows:1) Add VCS compile option “vcs -assert

2012-01-21 22:17:24 2769

原创 vmware修改MAC地址的方法

为了使用EDA tools, 有时候需要修改自己的MAC地址。我是用vmware的。尝试的结果如下：VMWARE中修改MAC地址的方法:1. 可以修改.vmx配置文件的MAC内容。（不可取）删除以下三行， ethernet[n].generatedAddress ethernet[n].addressType ethernet[n].gen

2011-12-22 16:28:03 5711

原创 MDIO master VIP 图解（ArrayBox的妙用）

如图： 1. readword 每调用一次，最后都会update RdDataPtr，使其自增1.2. 关联数组RdDataArrayBox， Index 是 RdDataPtr， Value 是各个mailbox。 mailbox中放入的是各个transaction。为何不直接将RdDataArrayBox的值设为各个transaction呢？这是个关键所在！不防考虑一下这种

2011-11-17 16:14:21 1513

原创 I2C VIP block diagram

Slave VIP 简单，只需要一块internal memory就成了，不需要InBox或者OutBox这样的mailbox。只不过，interface有点讲究interface i2c_s_if(inout tri1 sda); // I2C bus signals wire scl; // Tri-state buffer control logic s

2011-11-15 16:24:29 2504

原创 APB3.0 Slave Master VIP 框图

slave从OUT FIFO中拿到data后（阻塞语句），放到总线上，然后等待preadyDelay规定的cycle后将pready有效。pready有效后，可以随机撤销或者保持1的状态。slave从mem中拿到data后，放到总线上，然后等待preadyDelay规定的cycle后将pready有效。pready有效后，可以随机撤销或者保持1的状态。env中提供了访问InBox mail

2011-11-14 11:12:45 5703

转载 Smart Constraints In SystemVerilog

class frame; rand bit valid; constraint user_constraint; constraint user_prob { valid dist { 1:= 90, 0:= 10}; // default distribution // valid dist { 1:=

2011-11-11 10:51:54 2294

转载 QA in verification

Q6: Which of the parts in the testbench should add data to the scoreboard? A6: That’s a million dollar question…there are two main approaches and the decision between the two should be done accordin

2011-11-10 17:39:13 520

转载 Results Generaton - Environment or Test Generator?

Results Generaton - Environment or Test Generator?There are a variety of ways to do results checking in a testbench. They tend to fall into three categories.Tests generate expected results.

2011-11-10 17:38:18 597

转载 program interface module class 区别

来自于大牛 Specman Verification SV is a fact of life and is here to stay. You can feel happy or sad about it, think that it’s a big step to humanity, or a very small step towards standardization, eith

2011-11-10 10:41:05 3297

原创 AXI VIP Master

here is block diagram for AXI MASTER VIP.1. semaphore put-then-get can notify all previously queued task are finished. wait until wait transaction are executed. Just like sync or block instruction.

2011-11-08 18:19:33 3976

原创 SystemVerilog 中的 Variable slice of vector and array

///////////////////////////////////////////////////////////////////////////// /*- unpack2pack(): Convert unpack array to packed.*/ ///////////////////////////////////////////////////////////////

2011-11-07 15:46:12 1379