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A Verilog HDL Test Bench Primer
This applications note and the included Verilog source code describe how to apply
stimulus to a behavioral or gate level description of a CPLD design. The designer should
have access to a Verilog simulator and be familiar with its’ basic functionality. In short,
the Verilog code for each of the individual modules is compiled and the simulation is run.
By applying stimulus and simulating the design, the designer can be sure the correct
functionality of the design is achieved. This design uses a loadable 4-bit counter and test
bench to illustrate the basic elements of a Verilog simulation. The design is instantiated
in a test bench, stimulus is applied to the inputs, and the outputs are monitored for the
desired results.
2010-07-20
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