mengjin7210的专栏

1 Introduction..............................................................................................................................................10 1.1 SSIC Significant Features ................................................................................................................11 1.2 SSIC and Standard SuperSpeed Comparison.................................................................................11 1.3 Related Documents ..........................................................................................................................12 1.4 Terminology......................................................................................................................................12 1.5 Acronyms and Terms .......................................................................................................................12 2 Adaptation of M-PHY for the Physical Layer ........................................................................................14 2.1 M-PHY for SSIC Overview ...............................................................................................................14 2.2 M-PHY MODULE Capabilities..........................................................................................................14 2.3 M-PHY Configuration Attributes .......................................................................................................21 2.4 M-PHY State Machine......................................................................................................................22 2.5 LS-MODE Support............................................................................................................................22 3 Link Layer.................................................................................................................................................31 3.1 Bit and Byte Ordering .......................................................................................................................31 3.2 Logical Idle and FLR non-insertion...................................................................................................32 3.3 Line Coding ......................................................................................................................................33 3.4 Clock Compensation ........................................................................................................................34 3.5 Data Scrambling ...............................................................................................................................36 3.6 PowerOn Reset and Inband Reset...................................................................................................37 3.7 Link Layer Timing Requirements......................................................................................................38 3.8 SSIC Link Training and Status State Machine (LTSSM)..................................................................39 4 Protocol Layer..........................................................................................................................................51 4.1 Port Capability Link Management Packet (LMP) .............................................................................51 4.2 Timing Parameters ...........................................................................................................................51 5 Device Framework...................................................................................................................................53 5.1 Dynamic Attachment and Removal ..................................................................................................53 6 MPHY.TEST ..............................................................................................................................................55 6.1 Overview...........................................................................................................................................55 6.2 Entering MPHY.TEST.......................................................................................................................56 6.3 Loopback Testing .............................................................................................................................57 6.4 Receive Burst Testing ......................................................................................................................58 6.5 Tx Compliance Mode........................................................................................................................58 6.6 Analog Loopback Mode....................................................................................................................58 6.7 MPHY.TEST Block Registers...........................................................................................................59 7 Timing Diagrams Appendix (Informative) .........................................

Acknowledgement of USB 3.0 Technical Contribution 1 Introduction 1.1 Motivation.................................................................................................................1-1 1.2 Objective of the Specification...................................................................................1-2 1.3 Scope of the Document............................................................................................1-2 1.4 USB Product Compliance.........................................................................................1-2 1.5 Document Organization............................................................................................1-3 1.6 Design Goals............................................................................................................1-3 1.7 Related Documents..................................................................................................1-3 2 Terms and Abbreviations 3 SuperSpeed USB Architectural Overview 3.1 USB 3.0 Overview....................................................................................................3-1 3.1.1 SuperSpeed Architecture Overview........................................................3-2 3.1.1.1 Physical Layer.................................................................3-2 3.1.1.2 Link Layer........................................................................3-3 3.1.1.3 Protocol Layer.................................................................3-3 3.1.1.4 Hubs................................................................................3-4 3.1.1.5 Power Management........................................................3-5 3.2 USB 3.0 System.......................................................................................................3-5 3.2.1 Comparing SuperSpeed USB to USB 2.0 ..............................................3-5 3.2.2 System Level Topology ..........................................................................3-7 3.2.2.1 Hosts...............................................................................3-7 3.2.2.2 Hubs................................................................................3-8 3.2.2.3 Devices ...........................................................................3-8 3.2.3 Bus Protocol ...........................................................................................3-9 3.2.4 Robustness...........................................................................................3-10 3.2.4.1 Error Detection..............................................................3-10 3.2.4.2 Error Handling...............................................................3-10 3.3 USB Specification Chapter Overview.....................................................................3-11 3.3.1 Mechanical............................................................................................3-12 3.3.2 Physical Layer ......................................................................................3-14 3.3.3 Link Layer .............................................................................................3-15 3.3.4 Protocol Layer.......................................................................................3-15 3.3.5 Framework Layer..................................................................................3-16 3.3.6 Hubs .....................................................................................................3-16 3.3.6.1 Hub Architecture ...........................................................3-17 3.3.6.2 Hub Repeater/Forwarder Architecture ..........................3-18 3.3.6.3 Hubs and Transfers to Power Managed Links ..............3-18 3.3.7 Performance and Power Efficiency.......................................................3-18

ECM(太网控制模型)协议文档 The USB Communications Device Class Specification 1.1 contains general Communications Class specifications, and details for seven device subclasses. That specification has been editorially reorganized into a common USB CDC 1.2 specification [USBCDC1.2] and a set of subclass specifications. This should help implementers understand what is necessary for each device subclass and facilitate specification maintenance by the USB Device Working Group. This document is one of those subclass specifications. It contains material technically identical to that contained in USB CDC 1.1. It is intended to guide implementers of USB-connected devices of the types listed in the following section. 1.2 Scope This document specifies one device subclass intended for use with Communication devices, based on the Universal Serial Bus Class Definitions for Communication Devices specification [USBCDC1.2]. It supports Ethernet (IEEE 802.3) and similar devices. The intention of this specification is that all material presented here is technically compatible with the previous version of the USB CDC 1.1 Specification, from which it is derived. Numeric codes are defined for subclass codes, protocol codes, management elements, and notification elements. In some cases material from [USBCDC1.2] is repeated for clarity. In such cases, [USBCDC1.2] shall be treated as the controlling document. In this specification, the word ‘shall’ or ‘must’ is used for mandatory requirements, the word ‘should’ is used to express recommendations and the word ‘may’ is used for options.

深入理解Linux内核(第三版中文)主要介绍内核的基本知识，有利于需要学习Linux内核的同学更好的理解Linux内核 为了彻底理解是什么使得Linux能正常运行以及其为何能在各种不同的系统中运行良好，你需要深入研究内核最本质的部分。内核处理CPU与外界间的所有交互，并且决定哪些程序将以什么顺序共享处理器时间。它如此有效地管理有限的内存，以至成百上千的进程能高效地共享系统。它熟练地统筹数据传输，这样CPU不用为等待速度相对较慢的硬盘而消耗比正常耗时更长的时间。, 《深入理解Linux内核，第三版》指导你对内核中使用的最重要的数据结构、算法和程序设计诀窍进行一次遍历。通过对表面特性的探究，作者给那些想知道自己机器工作原理的人提供了颇有价值的见解。书中讨论了Intel特有的重要性质。相关的代码片段被逐行剖析。然而，本书涵盖的不仅仅是代码的功能，它解释了Linux以自己的方式工作的理论基础。, 本书将使你了解Linux的所有内部工作，它不仅仅是一个理论上的练习。你将学习到哪些情况下Linux性能最佳，并且你将看到，在大量的不同环境里进行进程调度、文件存取和内存管理时，它如何满足提供良好的系统响应的需要。这本书将帮助你充分利用Linux系统

MBIM是伴随着移动宽带在notebook/Ultrabook, Tablet, Pad等移动设备广泛应用，由Intel, Microsoft等多家USB/IF成员提出的一个新的接口标准。 它统一了移动宽带设备(USB 数据卡/上网卡之类，NGFF数据卡等) 和 PC端的接口标准。 Modem厂商不用再提供驱动，目前Win8上已经支持。 Linux 在3.8版本之后也会支持。 Win7开始引入了系统自带的移动宽带设备管理工具(即WWAN管理界面)。安装WWAN驱动后，系统WWAN管理界面会映射出该数据卡所对应的WWAN的Profile。用户从这个系统管理界面可以发起WWAN拨号或进行PIN码管理。 Win8扩展了这个系统自带的管理界面，允许更多的操作，如SMS、Phonebook、STK、USSD管理等。还允许第三方公司开发自己的类似功能并显示到这个管理界面，MBIM模型就是针对这种情况定义的接口规范。

此版本属于xshell 个人版，一个窗口只能打开4个session, 打开第5个session的时候，会自动打开另外一个窗口，基本满足目前的需求。

3. 蓝牙驱动介绍............................................................................................................................................... 4 3.1 串口驱动介绍........................................................................................................................................ 5 3.2 初始化.................................................................................................................................................... 5 3.2.1 模块上电........................................................................................................................................ 5 3.2.2 PSKEY的设置................................................................................................................................. 6 3.3 HCIATTACH的工作原理.......................................................................................................................... 7 3.3.1 Hci_uar和bcsp层的加入................................................................................................................. 9 3.3.2 hci层的加入.................................................................................................................................. 10 3.3.3 hci_attach的内核处理.................................................................................................................. 11 4. 数据在驱动的传递流程.............................................................................................................................. 13 4.1 UART层的数据接收.............................................................................................................................. 13 4.2 HCI_UART的数据接收.......................................................................................................................... 14 4.3 BCSP层的处理...................................................................................................................................... 15 4.4 HCI层及以上的处理............................................................................................................................. 15 4.5 数据流程的总结.................................................................................................................................. 17 5. 扫描过程的分析......................................................................................................................................... 18 5.1 用户使用例子...................................................................................................................................... 18 5.2 用HCITOOL扫描时的逻辑..................................................................................................................... 18 5.2.1 上层逻辑...................................................................................................................................... 18 5.2.2 内核层逻辑.................................................................................................................................. 19 5.3 通过DBUS触发的逻辑.......................................................................................................................... 21 5.3.1 上层逻辑之adapter dbus方法的建立........................................................................................... 21 5.3.2 上层扫描方法的调用................................................................................................................... 22 5.3.3 Dbus触发的扫描对应于内核层的处理........................................................................................ 25 5.3.4 上层的扫描数据收集................................................................................................................... 26 5.3.5 Hci_send_frame的讨论................................................................................................................. 28 6. A2DP的使用过程........................................................................................................................................ 28 6.1 如何使用.............................................................................................................................................. 28 6.2 服务的激活.......................................................................................................................................... 29 6.3 设备的创建.......................................................................................................................................... 30 6.3.1............................................................................................................................................................. 33 6.3.2............................................................................................................................................................. 33 6.3.3............................................................................................................................................................. 33 6.3.4............................................................................................................................................................. 33 6.4 设备的连接.......................................................................................................................................... 33