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原创图解 FPGA Architecture

图解 FPGA Architecture

2022-04-02 10:47:17 341

原创 Quartus Design Partition 原则

在介绍原则之前需要区分几个基本的概念：Design Partition 和 Logic LockDesign Partition 旨在设计逻辑分区而Logic Lock为物理分区。另外引申出一个概念: Incremental Compilation（增量式编译也被称为渐进式编译）：Logic Lock并非Incremental Compilation的一部分，而是Incremental Compilation时建议设计者使用Logic Lock，以此来提升Fmax。（有机会的话再来归纳..

2021-09-22 16:57:03 662

原创 Xilinx coe 与 Intel(Altera) mif 文件转化脚本

两种脚本方法：1：tcl# X_to_A_mif_conversion.tcl# This script will convert a Xilinx mif file to an Intel PSG (Altera) mif file# mif files are often used as initialization files for FPGA RAM implementations# # usage from a tcl console window in Quartus or f

2021-09-16 10:33:46 799

原创 Intel (Altera) LVDS

Altera的FPGA顶部、底部和左右侧会有真LVDS 输入缓冲器和LVDS I/O缓冲器。（不同封装不同系列的器件LVDS的位置，数量会有差异）LVDS 输入缓冲器支持具有100-Ω 的片上差分匹配(RD OCT)。可将LVDS I/O缓冲器配置成LVDS 输入( 不带RD OCT) 或者真LVDS 输出缓冲器。也可以将器件顶端、底部和右侧的LVDS 管脚配置成伪LVDS 输出缓冲器，把两个单端输出缓冲器和一个电路板上的电阻网络一起使用，来支持LVDS、mini- LVDS 和RSDS

2021-09-14 14:02:26 2547 2

Removing Ground Noise in Data Transmission Systems

This application report explains how electrical installation systems, wired correctly (or incorrectly), in combination with time-varying loads can create large GPDs between remote transceiver stations. It also explains the frequency content of GPDs and demonstrates how to isolate a data transmission system by avoiding ground loops and GPDs that might adversely affect the quality of the transmission signal. It provides product examples for increasing tolerance to GPDs.

2022-04-21