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Where such assertions are placed on the contents of a Dirac bitstream itself, implementations should be prepared to encounter

It provides information how to build the software on Windows 32/64 bit and Linux 32/64 bit platforms. It contains a description of the usage and configuration for the binaries built from the software package, including examples for spatial, SNR and combined scalability scenarios.

This study presents a fast video transcoding architecture that overcomes the complexity of different coding structures between H.264/AVC and SVC. The proposed algorithms simplify the mode decision process in SVC owing to its heavy computations. Two scenarios namely transcoding with the same quantization parameter and bitrate reduction are considered. In the first scenario, SVC’s modes are determined by the probability models, including

Single-instruction multiple-data (SIMD) accelerators provide an energy-efficient platform to scale the performance of mobile sys- tems while still retaining post-programmability. The central chal- lenge is translating the parallel resources of the SIMD hardware into real application performance.

In this paper, we we first propose a parallel video coding framework, where three important factors: parallel strategy, computation complexity and scheduling of tasks are considered. Then considering the characteristics of medium-grain quality scalability (MGS)-based Scalable Video Coding (SVC), a new layer-level parallel encoding method is also introduced. Since each encoding task could have different priority under different parallel strategy, the scheduling of layer-level parallel encoding tasks is extremely complex. We use Directed Acyclic Graph (DAG) to model the relationship of encoding tasks and theoretically analyze how to find the optimal solution. Then according to the DAG model, several heuristic scheduling methods are employed to get a high speed-up ratio. Experiments show the speedup of our layer-level parallel method was higher than the prior works. Using the proposed method High Definition (HD) SVC videos can be encoded in real time with SIMD technology.

The optimization process of a H.264/AVC encoder on three different architectures is presented. The architectures are multi- and singlecore and SIMD instruction sets have different vector registers size. The need of code optimization is fundamental when addressing HD resolutions with real-time constraints. The encoder is subdivided in functional modules in order to better understand where the optimization is a key factor and to evaluate in details the performance improvement. Common issues in both partitioning a video encoder into parallel architectures and SIMD optimization are described, and author solutions are presented for all the architectures. Besides showing efficient video encoder implementations, one of the main purposes of this paper is to discuss how the characteristics of different architectures and different set of SIMD instructions can impact on the target application performance. Results about the achieved speedup are provided in order to compare the different implementations and evaluate the more suitable solutions for present and next generation video-coding algorithms.