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步进电机VHDL程序
Directory/Files structure
project/
hdl - contains all source files (*.v)
Top Module - top_stepper_ip.v
Stimulus - contains test bench file (top_tb)
simulation - PRE-SYNTHESIS ONLY
run.do - this file contains the script for Modelsim Simulation Run
log file
wave.do
output work directory - presynth
To run Simulation:
In Project Manager:
Click on Simulation (Modelsim) Button to run Simulation
(The program executes run.do)
On modelsim prompt give command :
" run -all "
For s/w full step high rng with step,'Transcript' window will display
S/W clkwise full_step high-range test starts at Time = 2000000
S/W clkwise full_step high-range test ends at Time = 190161200000
S/W counter clkwise full_step high-range test starts at Time = 255161200000
S/W counter clkwise full_step high-range test ends at Time = 445320400000
For s/w full step low range with step,'Transcript' window will display
S/W clkwise full_step low-range test starts at Time = 2000000
S/W clkwise full_step low-range test ends at Time = 190161200000
S/W counter clkwise full_step low-range test starts at Time = 255161200000
S/W counter clkwise full_step low-range test ends at Time = 445320400000
For s/w half step low range with step,'Transcript' window will display
S/W clkwise half_step low-range test starts at Time = 2000000
S/W clkwise half_step low-range test ends at Time = 190161200000
S/W counter clkwise half_step low-range test starts at Time = 255161200000
S/W counter clkwise half_step low-range test ends at Time = 445320400000
For s/w half step high range with step,'Transcript' window will display
S/W clkwise half_step high-range test starts at Time = 2000000
S/W clkwise half_step high-range test ends at Time = 190161200000
S/W counter clkwise half_step high-range test starts at Time = 255161200000
S/W counter clkwise half_step high-range test ends at Time = 445320400000
For s/w for half step low range with step and plus_minus,'Transcript' window wi
2009-06-09
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