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Introduction to the Controller Area Network (CAN)
TI的CAN应用文档,英文,17页,结合TI的can 器件进行说明,对深入理解can总线协议有一定的帮助。
2023-08-15
Understanding and using the Controller Area Network
理解和使用CAN,英文版,作者Marco Di Natale,可与《CAN 入门书》结合起来看
2023-08-15
The Definitive Guide to ARM Cortex-M3 and Cortex-M4 Processors 3rd Edition
Cortex-M3-M4权威指南第三版 英文 PDF 每章节一个文件 非复印版 文字可拷贝
2018-06-19
See MIPS Run 2nd Edition for Linux
See MIPS® Run
Second Edition
Dominic Sweetman
English Version
PDF
2010-05-06
PCI Express Base Specification Revision 2.1
PCI Express Base Specification Revision 2.1
Contents
OBJECTIVE OF THE SPECIFICATION.................................................................................... 25
DOCUMENT ORGANIZATION ................................................................................................ 25
DOCUMENTATION CONVENTIONS...................................................................................... 26
TERMS AND ACRONYMS........................................................................................................ 27
REFERENCE DOCUMENTS...................................................................................................... 34
1. INTRODUCTION ................................................................................................................ 35
1.1. A THIRD GENERATION I/O INTERCONNECT ................................................................... 35
1.2. PCI EXPRESS LINK......................................................................................................... 37
1.3. PCI EXPRESS FABRIC TOPOLOGY .................................................................................. 39
1.3.1. Root Complex........................................................................................................ 39
1.3.2. Endpoints .............................................................................................................. 40
1.3.3. Switch.................................................................................................................... 43
1.3.4. Root Complex Event Collector.............................................................................. 44
1.3.5. PCI Express to PCI/PCI-X Bridge........................................................................ 44
1.4. PCI EXPRESS FABRIC TOPOLOGY CONFIGURATION....................................................... 44
1.5. PCI EXPRESS LAYERING OVERVIEW.............................................................................. 45
1.5.1. Transaction Layer................................................................................................. 46
1.5.2. Data Link Layer .................................................................................................... 46
1.5.3. Physical Layer ...................................................................................................... 47
1.5.4. Layer Functions and Services............................................................................... 47
2. TRANSACTION LAYER SPECIFICATION ..................................................................... 51
2.1. TRANSACTION LAYER OVERVIEW.................................................................................. 51
2.1.1. Address Spaces, Transaction Types, and Usage................................................... 52
2.1.2. Packet Format Overview ...................................................................................... 54
2.2. TRANSACTION LAYER PROTOCOL - PACKET DEFINITION............................................... 56
2.2.1. Common Packet Header Fields ............................................................................ 56
2.2.2. TLPs with Data Payloads - Rules ......................................................................... 59
2.2.3. TLP Digest Rules .................................................................................................. 63
2.2.4. Routing and Addressing Rules.............................................................................. 63
2.2.5. First/Last DW Byte Enables Rules........................................................................ 67
2.2.6. Transaction Descriptor......................................................................................... 70
2.2.7. Memory, I/O, and Configuration Request Rules................................................... 75
2.2.8. Message Request Rules......................................................................................... 81
2.2.9. Completion Rules.................................................................................................. 94
2.2.10. TLP Prefix Rules................................................................................................... 97
2.3. HANDLING OF RECEIVED TLPS.................................................................................... 101
2.3.1. Request Handling Rules...................................................................................... 104
2.3.2. Completion Handling Rules................................................................................ 117
2.4. TRANSACTION ORDERING............................................................................................ 119
2.4.1. Transaction Ordering Rules ............................................................................... 119
2.4.2. Update Ordering and Granularity Observed by a Read Transaction ................ 123
2.4.3. Update Ordering and Granularity Provided by a Write Transaction ................ 124
2.5. VIRTUAL CHANNEL (VC) MECHANISM........................................................................ 125
2.5.1. Virtual Channel Identification (VC ID) .............................................................. 127
2.5.2. TC to VC Mapping.............................................................................................. 128
2.5.3. VC and TC Rules................................................................................................. 129
2.6. ORDERING AND RECEIVE BUFFER FLOW CONTROL ..................................................... 130
2.6.1. Flow Control Rules............................................................................................. 131
2.7. DATA INTEGRITY ......................................................................................................... 141
2.7.1. ECRC Rules ........................................................................................................ 142
2.7.2. Error Forwarding ............................................................................................... 146
2.8. COMPLETION TIMEOUT MECHANISM........................................................................... 148
2.9. LINK STATUS DEPENDENCIES ...................................................................................... 149
2.9.1. Transaction Layer Behavior in DL_Down Status............................................... 149
2.9.2. Transaction Layer Behavior in DL_Up Status ................................................... 150
DATA LINK LAYER SPECIFICATION.......................................................................... 151
3.1. DATA LINK LAYER OVERVIEW .................................................................................... 151
3.2. DATA LINK CONTROL AND MANAGEMENT STATE MACHINE ...................................... 153
3.2.1. Data Link Control and Management State Machine Rules ................................ 154
3.3. FLOW CONTROL INITIALIZATION PROTOCOL ............................................................... 156
3.3.1. Flow Control Initialization State Machine Rules ............................................... 156
3.4. DATA LINK LAYER PACKETS (DLLPS)........................................................................ 160
3.4.1. Data Link Layer Packet Rules ............................................................................ 160
3.5. DATA INTEGRITY ......................................................................................................... 165
3.5.1. Introduction......................................................................................................... 165
3.5.2. LCRC, Sequence Number, and Retry Management (TLP Transmitter).............. 165
3.5.3. LCRC and Sequence Number (TLP Receiver) .................................................... 178
PHYSICAL LAYER SPECIFICATION............................................................................ 187
4.1. INTRODUCTION ............................................................................................................ 187
4.2. LOGICAL SUB-BLOCK................................................................................................... 187
4.2.1. Symbol Encoding ................................................................................................ 188
4.2.2. Framing and Application of Symbols to Lanes................................................... 191
4.2.3. Data Scrambling ................................................................................................. 194
4.2.4. Link Initialization and Training.......................................................................... 196
4.2.5. Link Training and Status State Machine (LTSSM) Descriptions........................ 208
4.2.6. Link Training and Status State Rules.................................................................. 212
4.2.7. Clock Tolerance Compensation.......................................................................... 258
4.2.8. Compliance Pattern ............................................................................................ 260
4.2.9. Modified Compliance Pattern............................................................................. 261
4.3. ELECTRICAL SUB-BLOCK ............................................................................................. 262
4.3.1. Maintaining Backwards Compatibility ............................................................... 262
4.3.2. Jitter Budgeting and Measurement..................................................................... 264
4.3.3. Transmitter Specification.................................................................................... 265
4.3.4. Receiver Specification......................................................................................... 281
4.3.5. Transmitter and Receiver DC Specifications...................................................... 293
4.3.6. Channel Specifications........................................................................................ 298
4.3.7. Reference Clock Specifications........................................................................... 305
5. POWER MANAGEMENT................................................................................................. 313
5.1. OVERVIEW ................................................................................................................... 313
5.1.1. Statement of Requirements.................................................................................. 314
5.2. LINK STATE POWER MANAGEMENT............................................................................. 314
5.3. PCI-PM SOFTWARE COMPATIBLE MECHANISMS......................................................... 319
5.3.1. Device Power Management States (D-States) of a Function.............................. 319
5.3.2. PM Software Control of the Link Power Management State.............................. 323
5.3.3. Power Management Event Mechanisms ............................................................. 329
5.4. NATIVE PCI EXPRESS POWER MANAGEMENT MECHANISMS....................................... 336
5.4.1. Active State Power Management (ASPM) .......................................................... 336
5.5. AUXILIARY POWER SUPPORT....................................................................................... 353
5.5.1. Auxiliary Power Enabling................................................................................... 353
5.6. POWER MANAGEMENT SYSTEM MESSAGES AND DLLPS............................................. 354
6. SYSTEM ARCHITECTURE ............................................................................................. 357
6.1. INTERRUPT AND PME SUPPORT ................................................................................... 357
6.1.1. Rationale for PCI Express Interrupt Model........................................................ 357
6.1.2. PCI Compatible INTx Emulation........................................................................ 358
6.1.3. INTx Emulation Software Model ........................................................................ 358
6.1.4. Message Signaled Interrupt (MSI/MSI-X) Support............................................. 358
6.1.5. PME Support....................................................................................................... 360
6.1.6. Native PME Software Model .............................................................................. 360
6.1.7. Legacy PME Software Model ............................................................................. 361
6.1.8. Operating System Power Management Notification........................................... 361
6.1.9. PME Routing Between PCI Express and PCI Hierarchies ................................ 361
6.2. ERROR SIGNALING AND LOGGING................................................................................ 362
6.2.1. Scope................................................................................................................... 362
6.2.2. Error Classification ............................................................................................ 362
6.2.3. Error Signaling ................................................................................................... 364
6.2.4. Error Logging ..................................................................................................... 371
6.2.5. Sequence of Device Error Signaling and Logging Operations .......................... 376
6.2.6. Error Message Controls ..................................................................................... 378
6.2.7. Error Listing and Rules ...................................................................................... 379
6.2.8. Virtual PCI Bridge Error Handling.................................................................... 384
6.2.9. Internal Errors.................................................................................................... 386
6.3. VIRTUAL CHANNEL SUPPORT ...................................................................................... 386
6.3.1. Introduction and Scope ....................................................................................... 386
6.3.2. TC/VC Mapping and Example Usage................................................................. 387
6.3.3. VC Arbitration .................................................................................................... 389
6.3.4. Isochronous Support ........................................................................................... 397
6.4. DEVICE SYNCHRONIZATION......................................................................................... 400
6.5. LOCKED TRANSACTIONS.............................................................................................. 401
6.5.1. Introduction......................................................................................................... 401
6.5.2. Initiation and Propagation of Locked Transactions - Rules............................... 402
6.5.3. Switches and Lock - Rules................................................................................... 403
6.5.4. PCI Express/PCI Bridges and Lock - Rules ....................................................... 403
6.5.5. Root Complex and Lock - Rules.......................................................................... 404
6.5.6. Legacy Endpoints................................................................................................ 404
6.5.7. PCI Express Endpoints ....................................................................................... 404
6.6. PCI EXPRESS RESET - RULES....................................................................................... 404
6.6.1. Conventional Reset ............................................................................................. 404
6.6.2. Function-Level Reset (FLR)................................................................................ 407
6.7. PCI EXPRESS HOT-PLUG SUPPORT .............................................................................. 410
6.7.1. Elements of Hot-Plug.......................................................................................... 411
6.7.2. Registers Grouped by Hot-Plug Element Association........................................ 417
6.7.3. PCI Express Hot-Plug Events............................................................................. 419
6.7.4. Firmware Support for Hot-Plug ......................................................................... 422
6.8. POWER BUDGETING CAPABILITY ................................................................................. 422
6.8.1. System Power Budgeting Process Recommendations......................................... 423
6.9. SLOT POWER LIMIT CONTROL ..................................................................................... 423
6.10. ROOT COMPLEX TOPOLOGY DISCOVERY................................................................. 426
6.11. LINK SPEED MANAGEMENT ..................................................................................... 428
6.12. ACCESS CONTROL SERVICES (ACS) ........................................................................ 429
6.12.1. ACS Component Capability Requirements ......................................................... 430
6.12.2. Interoperability ................................................................................................... 434
6.12.3. ACS Peer-to-Peer Control Interactions.............................................................. 435
6.12.4. ACS Violation Error Handling ........................................................................... 435
6.12.5. ACS Redirection Impacts on Ordering Rules ..................................................... 436
6.13. ALTERNATIVE ROUTING-ID INTERPRETATION (ARI) .............................................. 438
6.14. MULTICAST OPERATIONS......................................................................................... 442
6.14.1. Multicast TLP Processing................................................................................... 442
6.14.2. Multicast Ordering.............................................................................................. 445
6.14.3. Multicast Capability Structure Field Updates.................................................... 445
6.14.4. MC Blocked TLP Processing.............................................................................. 446
6.14.5. MC_Overlay Mechanism .................................................................................... 446
6.15. ATOMIC OPERATIONS (ATOMICOPS) ....................................................................... 450
6.15.1. AtomicOp Use Models and Benefits ................................................................... 451
6.15.2. AtomicOp Transaction Protocol Summary......................................................... 451
6.15.3. Root Complex Support for AtomicOps................................................................ 453
6.15.4. Switch Support for AtomicOps............................................................................ 455
6.16. DYNAMIC POWER ALLOCATION (DPA) CAPABILITY ............................................... 455
6.16.1. DPA Capability with Multi-Function Devices.................................................... 456
6.17. TLP PROCESSING HINTS (TPH) ............................................................................... 457
6.17.1. Processing Hints ................................................................................................. 457
6.17.2. Steering Tags ...................................................................................................... 457
6.17.3. ST Modes of Operation ....................................................................................... 458
6.17.4. TPH Capability ................................................................................................... 459
6.18. LATENCY TOLERANCE REPORTING (LTR) MECHANISM .......................................... 460
7. SOFTWARE INITIALIZATION AND CONFIGURATION............................................ 467
7.1. CONFIGURATION TOPOLOGY........................................................................................ 467
7.2. PCI EXPRESS CONFIGURATION MECHANISMS ............................................................. 468
7.2.1. PCI 3.0 Compatible Configuration Mechanism ................................................. 469
7.2.2. PCI Express Enhanced Configuration Access Mechanism (ECAM).................. 470
7.2.3. Root Complex Register Block ............................................................................. 474
7.3. CONFIGURATION TRANSACTION RULES....................................................................... 475
7.3.1. Device Number.................................................................................................... 475
7.3.2. Configuration Transaction Addressing............................................................... 476
7.3.3. Configuration Request Routing Rules................................................................. 476
7.3.4. PCI Special Cycles.............................................................................................. 477
7.4. CONFIGURATION REGISTER TYPES .............................................................................. 478
7.5. PCI-COMPATIBLE CONFIGURATION REGISTERS........................................................... 479
7.5.1. Type 0/1 Common Configuration Space............................................................. 480
7.5.2. Type 0 Configuration Space Header................................................................... 487
7.5.3. Type 1 Configuration Space Header................................................................... 488
7.6. PCI POWER MANAGEMENT CAPABILITY STRUCTURE.................................................. 492
7.7. MSI AND MSI-X CAPABILITY STRUCTURES ................................................................ 494
7.7.1. Vector Control for MSI-X Table Entries............................................................. 494
7.8. PCI EXPRESS CAPABILITY STRUCTURE........................................................................ 495
7.8.1. PCI Express Capability List Register (Offset 00h) ............................................. 496
7.8.2. PCI Express Capabilities Register (Offset 02h) ................................................. 497
7.8.3. Device Capabilities Register (Offset 04h) .......................................................... 499
7.8.4. Device Control Register (Offset 08h) ................................................................. 504
7.8.5. Device Status Register (Offset 0Ah).................................................................... 510
7.8.6. Link Capabilities Register (Offset 0Ch).............................................................. 513
7.8.7. Link Control Register (Offset 10h) ..................................................................... 517
7.8.8. Link Status Register (Offset 12h) ........................................................................ 525
7.8.9. Slot Capabilities Register (Offset 14h) ............................................................... 528
7.8.10. Slot Control Register (Offset 18h) ...................................................................... 530
7.8.11. Slot Status Register (Offset 1Ah)......................................................................... 534
7.8.12. Root Control Register (Offset 1Ch) .................................................................... 536
7.8.13. Root Capabilities Register (Offset 1Eh) ............................................................. 538
7.8.14. Root Status Register (Offset 20h)........................................................................ 538
7.8.15. Device Capabilities 2 Register (Offset 24h) ....................................................... 539
7.8.16. Device Control 2 Register (Offset 28h) .............................................................. 543
7.8.17. Device Status 2 Register (Offset 2Ah)................................................................. 546
7.8.18. Link Capabilities 2 Register (Offset 2Ch)........................................................... 547
7.8.19. Link Control 2 Register (Offset 30h) .................................................................. 547
7.8.20. Link Status 2 Register (Offset 32h) ..................................................................... 551
7.8.21. Slot Capabilities 2 Register (Offset 34h) ............................................................ 551
7.8.22. Slot Control 2 Register (Offset 38h) ................................................................... 552
7.8.23. Slot Status 2 Register (Offset 3Ah)...................................................................... 552
7.9. PCI EXPRESS EXTENDED CAPABILITIES....................................................................... 552
7.9.1. Extended Capabilities in Configuration Space................................................... 553
7.9.2. Extended Capabilities in the Root Complex Register Block............................... 553
7.9.3. PCI Express Extended Capability Header.......................................................... 553
7.10. ADVANCED ERROR REPORTING CAPABILITY ........................................................... 554
7.10.1. Advanced Error Reporting Extended Capability Header (Offset 00h)............... 555
7.10.2. Uncorrectable Error Status Register (Offset 04h).............................................. 556
7.10.3. Uncorrectable Error Mask Register (Offset 08h)............................................... 558
7.10.4. Uncorrectable Error Severity Register (Offset 0Ch).......................................... 560
7.10.5. Correctable Error Status Register (Offset 10h).................................................. 562
7.10.6. Correctable Error Mask Register (Offset 14h)................................................... 563
7.10.7. Advanced Error Capabilities and Control Register (Offset 18h) ....................... 564
7.10.8. Header Log Register (Offset 1Ch) ...................................................................... 565
7.10.9. Root Error Command Register (Offset 2Ch) ...................................................... 566
7.10.10. Root Error Status Register (Offset 30h).......................................................... 567
7.10.11. Error Source Identification Register (Offset 34h) .......................................... 570
7.10.12. TLP Prefix Log Register (Offset 38h) ............................................................. 570
7.11. VIRTUAL CHANNEL CAPABILITY ............................................................................. 571
7.11.1. Virtual Channel Extended Capability Header.................................................... 573
7.11.2. Port VC Capability Register 1 ............................................................................ 574
7.11.3. Port VC Capability Register 2 ............................................................................ 575
7.11.4. Port VC Control Register.................................................................................... 576
7.11.5. Port VC Status Register ...................................................................................... 577
7.11.6. VC Resource Capability Register ....................................................................... 578
7.11.7. VC Resource Control Register............................................................................ 580
7.11.8. VC Resource Status Register .............................................................................. 582
7.11.9. VC Arbitration Table .......................................................................................... 583
7.11.10. Port Arbitration Table .................................................................................... 584
7.12. DEVICE SERIAL NUMBER CAPABILITY..................................................................... 586
7.12.1. Device Serial Number Extended Capability Header (Offset 00h) ...................... 587
7.12.2. Serial Number Register (Offset 04h)................................................................... 588
7.13. PCI EXPRESS ROOT COMPLEX LINK DECLARATION CAPABILITY ............................ 588
7.13.1. Root Complex Link Declaration Extended Capability Header........................... 590
7.13.2. Element Self Description..................................................................................... 591
7.13.3. Link Entries......................................................................................................... 592
7.14. PCI EXPRESS ROOT COMPLEX INTERNAL LINK CONTROL CAPABILITY................... 596
7.14.1. Root Complex Internal Link Control Extended Capability Header.................... 596
7.14.2. Root Complex Link Capabilities Register........................................................... 597
7.14.3. Root Complex Link Control Register.................................................................. 600
7.14.4. Root Complex Link Status Register..................................................................... 601
7.15. POWER BUDGETING CAPABILITY............................................................................. 602
7.15.1. Power Budgeting Extended Capability Header (Offset 00h).............................. 603
7.15.2. Data Select Register (Offset 04h) ....................................................................... 603
7.15.3. Data Register (Offset 08h).................................................................................. 604
7.15.4. Power Budget Capability Register (Offset 0Ch)................................................. 606
7.16. ACS EXTENDED CAPABILITY .................................................................................. 607
7.16.1. ACS Extended Capability Header (Offset 00h) .................................................. 607
7.16.2. ACS Capability Register (Offset 04h) ................................................................. 608
7.16.3. ACS Control Register (Offset 06h) ..................................................................... 609
7.16.4. Egress Control Vector (Offset 08h) .................................................................... 611
7.17. PCI EXPRESS ROOT COMPLEX EVENT COLLECTOR ENDPOINT ASSOCIATION
CAPABILITY ............................................................................................................................. 612
7.17.1. Root Complex Event Collector Endpoint Association Extended Capability
Header ............................................................................................................................. 613
7.17.2. Association Bitmap for Root Complex Integrated Endpoints............................. 614
7.18. MULTI-FUNCTION VIRTUAL CHANNEL CAPABILITY ................................................ 614
7.18.1. MFVC Extended Capability Header................................................................... 615
7.18.2. Port VC Capability Register 1 ............................................................................ 616
7.18.3. Port VC Capability Register 2 ............................................................................ 618
7.18.4. Port VC Control Register.................................................................................... 619
7.18.5. Port VC Status Register ...................................................................................... 620
7.18.6. VC Resource Capability Register ....................................................................... 620
7.18.7. VC Resource Control Register............................................................................ 622
7.18.8. VC Resource Status Register .............................................................................. 624
7.18.9. VC Arbitration Table .......................................................................................... 625
7.18.10. Function Arbitration Table ............................................................................. 625
7.19. VENDOR-SPECIFIC CAPABILITY ............................................................................... 627
7.19.1. Vendor-Specific Extended Capability Header (Offset 00h)................................ 628
7.19.2. Vendor-Specific Header (Offset 04h).................................................................. 629
7.20. RCRB HEADER CAPABILITY ................................................................................... 630
7.20.1. RCRB Header Extended Capability Header (Offset 00h)................................... 630
7.20.2. Vendor ID (Offset 04h) and Device ID (Offset 06h)........................................... 631
7.20.3. RCRB Capabilities (Offset 08h).......................................................................... 632
7.20.4. RCRB Control (Offset 0Ch) ................................................................................ 632
7.21. MULTICAST CAPABILITY ......................................................................................... 633
7.21.1. Multicast Extended Capability Header (Offset 00h) .......................................... 633
7.21.2. Multicast Capability Register (Offset 04h) ......................................................... 634
7.21.3. Multicast Control Register (Offset 06h) ............................................................. 635
7.21.4. Multicast Base Address Register (Offset 08h) .................................................... 636
7.21.5. MC_Receive Register (Offset 10h)...................................................................... 636
7.21.6. MC_Block_All Register (Offset 18h) .................................................................. 637
7.21.7. MC_Block_Untranslated Register (Offset 20h).................................................. 638
7.21.8. MC_Overlay_BAR (Offset 28h) .......................................................................... 638
7.22. RESIZABLE BAR CAPABILITY.................................................................................. 639
7.22.1. Resizable BAR Extended Capability Header (Offset 00h).................................. 641
7.22.2. Resizable BAR Capability Register (Offset 04h) ................................................ 642
7.22.3. Resizable BAR Control Register (Offset 08h)..................................................... 643
7.23. ARI CAPABILITY ..................................................................................................... 644
7.23.1. ARI Capability Header (Offset 00h) ................................................................... 645
7.23.2. ARI Capability Register (Offset 04h).................................................................. 645
7.23.3. ARI Control Register (Offset 06h) ...................................................................... 646
7.24. DYNAMIC POWER ALLOCATION (DPA) CAPABILITY ............................................... 647
7.24.1. DPA Extended Capability Header (Offset 00h).................................................. 647
7.24.2. DPA Capability Register (Offset 04h) ................................................................ 648
7.24.3. DPA Latency Indicator Register (Offset 08h)..................................................... 649
7.24.4. DPA Status Register (Offset 0Ch)....................................................................... 649
7.24.5. DPA Control Register (Offset 0Eh) .................................................................... 650
7.24.6. DPA Power Allocation Array ............................................................................. 650
7.25. LATENCY TOLERANCE REPORTING (LTR) CAPABILITY........................................... 651
7.25.1. LTR Extended Capability Header (Offset 00h)................................................... 651
7.25.2. Max Snoop Latency Register (Offset 04h) .......................................................... 652
7.25.3. Max No-Snoop Latency Register (Offset 06h) .................................................... 652
7.26. TPH REQUESTER CAPABILITY ................................................................................. 653
7.26.1. TPH Requester Extended Capability Header (Offset 00h) ................................. 654
7.26.2. TPH Requester Capability Register (Offset 04h)................................................ 654
7.26.3. TPH Requester Control Register (Offset 08h) .................................................... 656
7.26.4. TPH ST Table (Starting from Offset 0Ch) .......................................................... 657
A. ISOCHRONOUS APPLICATIONS................................................................................... 659
A.1. INTRODUCTION ............................................................................................................ 659
A.2. ISOCHRONOUS CONTRACT AND CONTRACT PARAMETERS ........................................... 661
A.2.1. Isochronous Time Period and Isochronous Virtual Timeslot ............................. 662
A.2.2. Isochronous Payload Size ................................................................................... 663
A.2.3. Isochronous Bandwidth Allocation..................................................................... 663
A.2.4. Isochronous Transaction Latency....................................................................... 664
A.2.5. An Example Illustrating Isochronous Parameters.............................................. 665
A.3. ISOCHRONOUS TRANSACTION RULES........................................................................... 666
A.4. TRANSACTION ORDERING............................................................................................ 666
A.5. ISOCHRONOUS DATA COHERENCY............................................................................... 666
A.6. FLOW CONTROL........................................................................................................... 667
A.7. CONSIDERATIONS FOR BANDWIDTH ALLOCATION....................................................... 667
A.7.1. Isochronous Bandwidth of PCI Express Links.................................................... 667
A.7.2. Isochronous Bandwidth of Endpoints ................................................................. 667
A.7.3. Isochronous Bandwidth of Switches ................................................................... 667
A.7.4. Isochronous Bandwidth of Root Complex........................................................... 668
A.8. CONSIDERATIONS FOR PCI EXPRESS COMPONENTS..................................................... 668
A.8.1. An Endpoint as a Requester................................................................................ 668
A.8.2. An Endpoint as a Completer............................................................................... 668
A.8.3. Switches............................................................................................................... 669
A.8.4. Root Complex...................................................................................................... 670
B. SYMBOL ENCODING...................................................................................................... 671
C. PHYSICAL LAYER APPENDIX...................................................................................... 681
C.1. DATA SCRAMBLING ..................................................................................................... 681
D. REQUEST DEPENDENCIES............................................................................................ 687
E. ID-BASED ORDERING USAGE...................................................................................... 691
E.1. INTRODUCTION ............................................................................................................ 691
E.2. POTENTIAL BENEFITS WITH IDO USE .......................................................................... 692
E.2.1. Benefits for MFD/RP Direct Connect................................................................. 692
E.2.2. Benefits for Switched Environments ................................................................... 692
E.2.3. Benefits for Integrated Endpoints ....................................................................... 693
E.2.4. IDO Use in Conjunction with RO ....................................................................... 693
E.3. WHEN TO USE IDO...................................................................................................... 693
E.4. WHEN NOT TO USE IDO.............................................................................................. 694
E.4.1. When Not to Use IDO with Endpoints ................................................................ 694
E.4.2. When Not to Use IDO with Root Ports ............................................................... 694
E.5. SOFTWARE CONTROL OF IDO USE............................................................................... 695
E.5.1. Software Control of Endpoint IDO Use.............................................................. 695
E.5.2. Software Control of Root Port IDO Use............................................................. 696
F. MESSAGE CODE USAGE................................................................................................ 697
ACKNOWLEDGEMENTS........................................................................................................ 699
2010-04-25
ETSI-TS-102-027-03v030101p.pdf
Methods for Testing and Specification (MTS);
Conformance Test Specification for SIP (IETF RFC 3261);
Part 3: Abstract Test Suite (ATS) and partial Protocol
Implementation eXtra Information for Testing (PIXIT) proforma
2008-09-11
ETSI-TS-102-027-02v030101p.pdf
Methods for Testing and Specification (MTS);
Conformance Test Specification for SIP (IETF RFC 3261);
Part 2: Test Suite Structure and Test Purposes (TSS&TP)
2008-09-11
ETSI-TS-102-027-01v030101p.pdf
Methods for Testing and Specification (MTS);
Conformance Test Specification for SIP IETF RFC 3261;
Part 1: Protocol Implementation Conformance
Statement (PICS) proforma
2008-09-11
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