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S3C2440A英文原版用户手册，共595页。 S3C2440A 32-BIT CMOS MICROCONTROLLER USER'S MANUAL Revision 1

S3C44B0X用户手册,绝对英文原版官方资料.没有经过修改.绝对原版. 1 PRODUCT OVERVIEW INTRODUCTION SAMSUNG's S3C44B0X 16/32-bit RISC microprocessor is designed to provide a cost-effective and high performance micro-controller solution for hand-held devices and general applications. To reduce total system cost, S3C44B0X also provides the following: 8KB cache, optional internal SRAM, LCD controller, 2-channel UART with handshake, 4- channel DMA, System manager (chip select logic, FP/ EDO/SDRAM controller), 5-channel timers with PWM, I/O ports, RTC, 8-channel 10-bit ADC, IIC-BUS interface, IIS-BUS interface, Sync. SIO interface and PLL for clock. The S3C44B0X was developed using a ARM7TDMI core, 0.25 um CMOS standard cells, and a memory compiler. Its low-power, simple, elegant and fully static design is particularly suitable for cost-sensitive and power sensitive applications. Also S3C44B0X adopts a new bus architecture, SAMBA II (SAMSUNG ARM CPU embedded Microcontroller Bus Architecture). An outstanding feature of the S3C44B0X is its CPU core, a 16/32-bit ARM7TDMI RISC processor (66MHz) designed by Advanced RISC Machines, Ltd. The architectural enhancements of ARM7TDMI include the Thumb decompressor, an on-chip ICE breaker debug support, and a 32-bit hardware multiplier. By providing a complete set of common system peripherals, the S3C44B0X minimizes overall system costs and eliminates the need to configure additional components. The integrated on-chip functions that are described in this document are as follows: · 2.5V Static ARM7TDMI CPU core with 8KB cache . (SAMBA II bus architecture up to 66MHz) · External memory controller. (FP/EDO/SDRAM Control, Chip Select logic) · LCD controller (up to 256 color DSTN) with 1-ch LCD-dedicated DMA. · 2-ch general DMAs / 2-ch peripheral DMAs with external request pins · 2-ch UART with handshake(IrDA1.0, 16-byte FIFO) / 1-ch SIO · 1-ch multi-master IIC-BUS controller · 1-ch IIS-BUS controller · 5-ch PWM timers & 1-ch internal timer · Watch Dog Timer · 71 general purpose I/O ports / 8-ch external interrupt source · Power control: Normal, Slow, Idle, and Stop mode · 8-ch 10-bit ADC. · RTC with calendar function. · On-chip clock generator with PLL.

内 容 简 介 本书比较系统地介绍了互联网搜索引擎的工作原理、实现技术及其系统构建方案。全书分三篇共13章内容，从基本工作原理概述开始，到一个小型简单搜索引擎实现的具体细节，进而详细讨论了大规模分布式搜索引擎系统的设计要点及其关键技术；最后面向主题和个性化的Web信息服务，阐述了中文网页自动分类等技术及其应用。本书层次分明，由浅入深；既有深入的理论分析，也有大量的实验数据，具有学习和实用双重意义。 本书可作为高等院校计算机科学与技术、信息管理与信息系统、电子商务等专业的研究生或高年级本科生的教学参考书和技术资料，对广大从事网络技术、Web站点的管理、数字图书馆、Web挖掘等研究和应用开发的科技人员也有很大的参考价值。

UC/OS-II操作系统源码V2.76版 精炼可靠的嵌入式实时操作系统 C语言源程序

S3C2410数据手册 S3C2410资料\博创官方\芯片资料\um_s3c2410s_rev12_030428.pdf 英文原版资料,没有经过修改.绝对原版. Table of Contents Chapter 1 Product Overview Introduction.............................................................................................................................................1-1 Features .................................................................................................................................................1-2 Block Diagram ........................................................................................................................................1-5 Pin Assignments.....................................................................................................................................1-6 Signal Descriptions.........................................................................................................................1-20 S3C2410X Special Registers...........................................................................................................1-25 Chapter 2 Programmer's Model Overview ................................................................................................................................................2-1 Processor Operating States.............................................................................................................2-1 Switching State ...............................................................................................................................2-1 Memory Formats .............................................................................................................................2-1 Big-Endian Format ..........................................................................................................................2-2 Little-Endian Format........................................................................................................................2-2 Instruction Length...........................................................................................................................2-2 Operating Modes............................................................................................................................2-3 Registers........................................................................................................................................2-3 The Program Status Registers.........................................................................................................2-7 Exceptions .....................................................................................................................................2-10 Interrupt Latencies..........................................................................................................................2-15 Reset..............................................................................................................................................2-15 iv S3C2410X MICROPROCESSOR Table of Contents (Continued) Chapter 3 ARM Instruction Set Instruction Set Summay......................................................................................................................... 3-1 Format Summary ........................................................................................................................... 3-1 Instruction Summary....................................................................................................................... 3-2 The Condition Field................................................................................................................................ 3-4 Branch and Exchange (BX)..................................................................................................................... 3-5 Instruction Cycle Times .................................................................................................................. 3-5 Assembler Syntax.......................................................................................................................... 3-5 Using R15 As An Operand.............................................................................................................. 3-5 Branch and Branch With Link (B, BL)...................................................................................................... 3-7 The Link Bit ................................................................................................................................... 3-7 Instruction Cycle Times .................................................................................................................. 3-7 Assembler Syntax.......................................................................................................................... 3-8 Data Processing..................................................................................................................................... 3-9 Cpsr Flags..................................................................................................................................... 3-11 Shifts............................................................................................................................................. 3-12 Immediate Operand Rotates........................................................................................................... 3-16 Writing to R15 ............................................................................................................................... 3-16 Using R15 As an Operandy ............................................................................................................ 3-16 TEQ, TST, CMP and CMN Opcodes............................................................................................... 3-16 Instruction Cycle Times .................................................................................................................. 3-16 Assembler Syntax.......................................................................................................................... 3-17 Examples ...................................................................................................................................... 3-17 PSR Transfer (MRS, MSR)..................................................................................................................... 3-18 Operand Restrictions ...................................................................................................................... 3-18 Reserved Bits................................................................................................................................ 3-20 Examples ...................................................................................................................................... 3-20 Instruction Cycle Times .................................................................................................................. 3-20 Assembly Syntax........................................................................................................................... 3-21 Examples ...................................................................................................................................... 3-21 Multiply and Multiply-Accumulate (MUL, MLA) ........................................................................................ 3-22 CPSR Flags................................................................................................................................... 3-24 Instruction Cycle Times .................................................................................................................. 3-24 Assembler Syntax.......................................................................................................................... 3-24 Examples ...................................................................................................................................... 3-24 Multiply Long and Multiply-Accumulate Long (MULL, MLAL)................................................................... 3-25 Operand Restrictions ...................................................................................................................... 3-26 Cpsr Flags..................................................................................................................................... 3-26 Instruction Cycle Times .................................................................................................................. 3-26 Assembler Syntax.......................................................................................................................... 3-27 Examples ...................................................................................................................................... 3-27 S3C2410X MICROPROCESSOR v Table of Contents (Continued) Chapter 3 ARM Instruction Set (Continued) Single Data Transfer (LDR, STR).............................................................................................................3-28 Offsets and Auto-Indexing ...............................................................................................................3-29 Shifted Register Offset ....................................................................................................................3-29 Bytes and Words............................................................................................................................3-29 Use Of R15 ....................................................................................................................................3-31 Example:........................................................................................................................................3-31 Data Aborts ....................................................................................................................................3-31 Instruction Cycle Times ...................................................................................................................3-31 Assembler Syntax ...........................................................................................................................3-32 Examples .......................................................................................................................................3-33 Halfword and Signed Data Transfer (LDRH/STRH/LDRSB/LDRSH).........................................................3-34 Offsets and Auto-Indexing ...............................................................................................................3-35 Halfword Load And Stores...............................................................................................................3-36 Use of R15 .....................................................................................................................................3-37 Data Aborts ....................................................................................................................................3-37 Instruction Cycle Times ...................................................................................................................3-37 Assembler Syntax ...........................................................................................................................3-38 Examples .......................................................................................................................................3-39 Block Data Transfer (LDM, STM).............................................................................................................3-40 The Register List .............................................................................................................................3-40 Addressing Modes..........................................................................................................................3-41 Address Alignment ..........................................................................................................................3-41 Use of the S Bit ...............................................................................................................................3-43 Use of R15 as the Base...................................................................................................................3-43 Inclusion of the Base In the Register List .........................................................................................3-44 Data Aborts ....................................................................................................................................3-44 Instruction Cycle Times ...................................................................................................................3-44 Assembler Syntax ...........................................................................................................................3-45 Examples .......................................................................................................................................3-46 Single Data Swap (SWP).........................................................................................................................3-47 Bytes and Words............................................................................................................................3-47 Use of R15 .....................................................................................................................................3-48 Data Aborts ....................................................................................................................................3-48 Instruction Cycle Times ...................................................................................................................3-48 Assembler Syntax ...........................................................................................................................3-48 Software Interrupt (SWI) ..........................................................................................................................3-49 Return from the Supervisor .............................................................................................................3-49 Comment Field...............................................................................................................................3-49 Instruction Cycle Times ...................................................................................................................3-49 Assembler Syntax ...........................................................................................................................3-50 Coprocessor Data Operations (CDP) .......................................................................................................3-51 Coprocessor Instructions .................................................................................................................3-51 Instruction Cycle Times ...................................................................................................................3-52 Examples .......................................................................................................................................3-52 vi S3C2410X MICROPROCESSOR Table of Contents (Continued) Chapter 3 ARM Instruction Set (Continued) Coprocessor Data Transfers (LDC, STC) ................................................................................................ 3-53 The Coprocessor Fields.................................................................................................................. 3-54 Addressing Modes .......................................................................................................................... 3-54 Address Alignment ......................................................................................................................... 3-54 Data Aborts ................................................................................................................................... 3-54 Assembler Syntax.......................................................................................................................... 3-55 Examples ...................................................................................................................................... 3-55 Coprocessor Register Transfers (MRC, MCR) ................................................................................ 3-56 The Coprocessor Fields.................................................................................................................. 3-56 Transfers to R15............................................................................................................................ 3-57 Transfers from R15......................................................................................................................... 3-57 Instruction Cycle Times .................................................................................................................. 3-57 Assembler Syntax.......................................................................................................................... 3-57 Examples ...................................................................................................................................... 3-57 Undefined Instruction..................................................................................................................... 3-58 Instruction Cycle Times .................................................................................................................. 3-58 Assembler Syntax.......................................................................................................................... 3-58 Instruction Set Examples ................................................................................................................ 3-59 Using The Conditional Instructions.................................................................................................. 3-59 Pseudo-Random Binary Sequence Generator................................................................................. 3-61 Multiplication by Constant Using the Barrel Shifter.......................................................................... 3-61 Loading a Word from an Unknown Alignment................................................................................. 3-63 Chapter 4 THUMB Instruction Set THUMB Instruction Set Format ............................................................................................................... 4-1 Format Summary ........................................................................................................................... 4-2 Opcode Summary .......................................................................................................................... 4-3 Format 1: Move Shifted Register ............................................................................................................ 4-5 Operation ...................................................................................................................................... 4-5 Instruction Cycle Times .................................................................................................................. 4-6 Examples ...................................................................................................................................... 4-6 Format 2: Add/Subtract.......................................................................................................................... 4-7 Operation ...................................................................................................................................... 4-7 Instruction Cycle Times .................................................................................................................. 4-8 Examples ...................................................................................................................................... 4-8 Format 3: Move/Compare/Add/Subtract Immediate ................................................................................ 4-9 Operations..................................................................................................................................... 4-9 Instruction Cycle Times .................................................................................................................. 4-10 Examples ...................................................................................................................................... 4-10 Format 4: ALU Operations ...................................................................................................................... 4-11 Operation ...................................................................................................................................... 4-11 Instruction Cycle Times .................................................................................................................. 4-12 Examples ...................................................................................................................................... 4-12 S3C2410X MICROPROCESSOR vii Table of Contents (Continued) Chapter 4 THUMB Instruction Set (Continued) Format 5: Hi-Register Operations/Branch Exchange................................................................................4-13 Operation .......................................................................................................................................4-13 Instruction Cycle Times ...................................................................................................................4-14 The Bx Instruction ...........................................................................................................................4-14 Examples .......................................................................................................................................4-15 Using R15 As An Operand...............................................................................................................4-15 Format 6: Pc-Relative Load .....................................................................................................................4-16 Operation .......................................................................................................................................4-16 Instruction Cycle Times ...................................................................................................................4-17 Examples .......................................................................................................................................4-17 Format 7: Load/Store With Register Offset ..............................................................................................4-18 Operation .......................................................................................................................................4-19 Instruction Cycle Times ...................................................................................................................4-19 Examples .......................................................................................................................................4-19 Format 8: Load/Store Sign-Extended Byte/Halfword ................................................................................4-20 Operation .......................................................................................................................................4-20 Instruction Cycle Times ...................................................................................................................4-21 Examples .......................................................................................................................................4-21 Format 9: Load/Store With Immediate Offset...........................................................................................4-22 Operation .......................................................................................................................................4-23 Instruction Cycle Times ...................................................................................................................4-23 Examples .......................................................................................................................................4-23 Format 10: Load/Store Halfword ..............................................................................................................4-24 Operation .......................................................................................................................................4-24 Examples .......................................................................................................................................4-25 Format 11: Sp-Relative Load/Store..........................................................................................................4-26 Operation .......................................................................................................................................4-26 Instruction Cycle Times ...................................................................................................................4-27 Examples .......................................................................................................................................4-27 Format 12: Load Address........................................................................................................................4-28 Operation .......................................................................................................................................4-28 Instruction Cycle Times ...................................................................................................................4-29 Examples .......................................................................................................................................4-29 Format 13: Add Offset To Stack Pointer ..................................................................................................4-30 Operation .......................................................................................................................................4-30 Instruction Cycle Times ...................................................................................................................4-30 Examples .......................................................................................................................................4-30 Format 14: Push/Pop Registers ...............................................................................................................4-31 Operation .......................................................................................................................................4-31 Instruction Cycle Times ...................................................................................................................4-32 Examples .......................................................................................................................................4-32 Format 15: Multiple Load/Store................................................................................................................4-33 Operation .......................................................................................................................................4-33 Instruction Cycle Times ...................................................................................................................4-33 Examples .......................................................................................................................................4-33 viii S3C2410X MICROPROCESSOR Table of Contents (Continued) Chapter 4 THUMB Instruction Set (Continued) Format 16: Conditional Branch................................................................................................................ 4-34 Operation ...................................................................................................................................... 4-34 Instruction Cycle Times .................................................................................................................. 4-35 Examples ...................................................................................................................................... 4-35 Operation ...................................................................................................................................... 4-36 Instruction Cycle Times .................................................................................................................. 4-36 Examples ...................................................................................................................................... 4-36 Format 18: Unconditional Branch............................................................................................................ 4-37 Operation ...................................................................................................................................... 4-37 Examples ...................................................................................................................................... 4-37 Operation ...................................................................................................................................... 4-38 Instruction Cycle Times .................................................................................................................. 4-39 Examples ...................................................................................................................................... 4-39 Instruction Set Examples ........................................................................................................................ 4-40 Multiplication By a Constant Using Shifts and Adds ........................................................................ 4-40 General Purpose Signed Divide...................................................................................................... 4-41 Division by a Constant.................................................................................................................... 4-43 Chapter 5 Memory Controller Overview ............................................................................................................................................... 5-1 Function Description ............................................................................................................................... 5-3 Bank0 Bus Width........................................................................................................................... 5-3 Memory (SROM/SDRAM) Address Pin Connections....................................................................... 5-3 Sdram Bank Address Pin Connection ............................................................................................. 5-4 Nwait Pin Operation....................................................................................................................... 5-5 nXBREQ/nXBACK Pin Operation.................................................................................................... 5-6 Programmable Access Cycle.......................................................................................................... 5-11 Bus Width & Wait Control Register (BWSCON).............................................................................. 5-13 Bank Control Register (BANKCONN: nGCS0-nGCS5).................................................................... 5-15 Bank Control Register (BANKCONn: nGCS6-nGCS7) .................................................................... 5-16 Refresh Control Register ................................................................................................................ 5-17 Banksize Register.......................................................................................................................... 5-18 SDRAM Mode Register Set Register (MRSR)................................................................................. 5-19 S3C2410X MICROPROCESSOR ix Table of Contents (Continued) Chapter 6 NAND Flash Controller Overview ................................................................................................................................................6-1 Features.........................................................................................................................................6-1 Block Diagram................................................................................................................................6-2 Operation Scheme ..........................................................................................................................6-2 Auto Boot Mode Sequence..............................................................................................................6-3 Nand Flash Mode Configuration ......................................................................................................6-3 Nand Flash Memory Timing ............................................................................................................6-3 Pin Configuration............................................................................................................................6-4 Boot and Nand Flash Configurations ...............................................................................................6-4 512-Byte ECC Parity Code Assignment Table .................................................................................6-4 Special Function Registers ......................................................................................................................6-6 Nand Flash Configuration (NFCONF) Register ................................................................................6-6 Nand Flash Command Set (NFCMD) Register.................................................................................6-7 Nand Flash Address Set (NFADDR) Register ..................................................................................6-7 Nand Flash Data (NFDATA) Register ..............................................................................................6-7 Nand Flash Operation Status (NFSTAT) Register............................................................................6-8 Nand Flash ECC (NFECC) Register ................................................................................................6-8 Chapter 7 Clock & Power Management Overview ................................................................................................................................................7-1 Functional Description .............................................................................................................................7-2 Clock Architecture ...........................................................................................................................7-2 Clock Source Selection ...................................................................................................................7-2 Phase Locked Loop (PLL) ...............................................................................................................7-4 Clock Control Logic .........................................................................................................................7-6 Power Management ........................................................................................................................7-9 Clock Generator & Power Management Special Register.........................................................................7-19 Lock Time Count Register (LOCKTIME)..........................................................................................7-19 PLL Value Selection Table ..............................................................................................................7-20 Clock Control Register (CLKCON)...................................................................................................7-21 Clock Slow Control (CLKSLOW) Register........................................................................................7-22 Clock Divider Control (CLKDIVN) Register ......................................................................................7-22 x S3C2410X MICROPROCESSOR Table of Contents (Continued) Chapter 8 DMA Overview ............................................................................................................................................... 8-1 DMA Request Sources........................................................................................................................... 8-2 DMA Operation ...................................................................................................................................... 8-2 Examples ...................................................................................................................................... 8-6 DMA Special Registers ........................................................................................................................... 8-7 DMA Initial Source (DISRC) Register.............................................................................................. 8-7 DMA Initial Source Control (DISRCC) Register............................................................................... 8-7 DMA Initial Destination (DIDST) Register ....................................................................................... 8-8 DMA Initial Destination Control (DIDSTC) Register......................................................................... 8-8 DMA Control (DCON) Register ....................................................................................................... 8-9 DMA Status (DSTAT) Register ....................................................................................................... 8-11 DMA Current Source (DCSRC) Register......................................................................................... 8-11 Current Destination (DCDST) Register ........................................................................................... 8-12 DMA Mask Trigger (DMASKTRIG) Register.................................................................................... 8-13 Chapter 9 I/O ports Overview ............................................................................................................................................... 9-1 Port Control Descriptions ........................................................................................................................ 9-7 Port Configuration Register (GPACON-GPHCON).......................................................................... 9-7 Port Data Register (GPADAT-GPHDAT)......................................................................................... 9-7 Port Pull-Up Register (GPBUP-GPHUP)......................................................................................... 9-7 Miscellaneous Control Register....................................................................................................... 9-7 External Interrupt Control Register (EXTINTN) ............................................................................... 9-7 Power_Off Mode and I/O Ports....................................................................................................... 9-7 I/O Port Control Register........................................................................................................................ 9-8 Port A Control Registers (GPACON/GPADAT) ............................................................................... 9-8 Port B Control Registers (GPBCON, GPBDAT, and GPBUP) ......................................................... 9-9 Port C Control Registers (GPCCON, GPCDAT, and GPCUP)......................................................... 9-10 Port D Control Registers (GPDCON, GPDDAT, and GPDUP)......................................................... 9-12 Port E Control Registers (GPECON, GPEDAT, and GPEUP) ......................................................... 9-14 Port F Control Registers (GPFCON, GPFDAT, and GPFPU).......................................................... 9-16 Port G Control Registers (GPGCON, GPGDAT, AND GPGUP)...................................................... 9-17 Port H Control Registers (GPHCON, GPHDAT, AND GPHUP)....................................................... 9-19 Miscellaneous Control Register (MISCCR) ..................................................................................... 9-20 DCLK Control Registers (DCLKCON) ............................................................................................. 9-21 External Interrupt Control Register (EXTINTn) ................................................................................ 9-22 External Interrupt Filter Register (EINTFLTn) ................................................................................. 9-25 External Interrupt Mask Register (EINTMASK) ............................................................................... 9-26 External Interrupt Pending Register (EINTPENDn) ........................................................................ 9-27 General Status Register (GSTATUSn)............................................................................................ 9-28 S3C2410X MICROPROCESSOR xi Table of Contents (Continued) Chapter 10 PWM Timer Overview ................................................................................................................................................10-1 PWM Timer Operation............................................................................................................................10-3 Prescaler & Divider .........................................................................................................................10-3 Auto Reload & Double Buffering......................................................................................................10-4 Timer Initialization Using Manual Update Bit and Inverter Bit ..........................................................10-5 Timer Operation ..............................................................................................................................10-6 Pulse Width Modulation (PWM).......................................................................................................10-7 Output Level Control .......................................................................................................................10-8 Dead Zone Generator......................................................................................................................10-9 Dma Request Mode.........................................................................................................................10-10 PWM Timer Control Registers .................................................................................................................10-11 Timer Configuration Register0 (TCFG0) ..........................................................................................10-11 Timer Configuration Register1 (TCFG1) ..........................................................................................10-12 Timer Control (TCON) Register .......................................................................................................10-13 Timer 0 Count Buffer Register & Compare Buffer Register (TCNTB0/TCMPB0)..............................10-15 Timer 1 Count Buffer Register & Compare Buffer Register (TCNTB1/TCMPB1)..............................10-16 Timer 2 Count Buffer Register & Compare Buffer Register (TCNTB2/TCMPB2)..............................10-17 Timer 3 Count Buffer Register & Compare Buffer Register (TCNTB3/TCMPB3)..............................10-18 Timer 3 Count Observation Register (TCNTO3) ..............................................................................10-18 Timer 4 Count Buffer Register (TCNTB4) ........................................................................................10-19 Chapter 11 UART Overview ................................................................................................................................................11-1 Features.........................................................................................................................................11-1 Block Diagram ........................................................................................................................................11-2 UART Operation.............................................................................................................................11-3 UART Special Registers ..........................................................................................................................11-10 UART Line Control Register ............................................................................................................11-10 UART Control Register....................................................................................................................11-11 UART FIFO Control Register...........................................................................................................11-13 UART Modem Control Register .......................................................................................................11-14 UART Tx/Rx Status Register ...........................................................................................................11-15 UART Error Status Register.............................................................................................................11-16 UART FIFO Status Register ............................................................................................................11-17 UART Modem Status Register.........................................................................................................11-18 UART Transmit Buffer Register (Holding Register & FIFO Register)................................................11-19 UART Receive Buffer Register (Holding Register & FIFO Register) ................................................11-19 UART Baud Rate Divisor Register...................................................................................................11-20 xii S3C2410X MICROPROCESSOR Table of Contents (Continued) Chapter 12 USB Host Controller Overview ............................................................................................................................................... 12-1 USB Host Controller Special Registers ........................................................................................... 12-2 Chapter 13 USB Device Overview ............................................................................................................................................... 13-1 Feature.......................................................................................................................................... 13-1 USB Device Controller Special Registers................................................................................................ 13-3 Function Address Register (FUNC_ADDR_REG)............................................................................ 13-5 Power Management Register (PWR_REG)..................................................................................... 13-6 Interrupt Register (EP_INT_REG/USB_INT_REG) ......................................................................... 13-7 Interrupt Enable Register (EP_INT_EN_REG/USB_INT_REG)....................................................... 13-9 Frame Number Register (FPAME_NUM1_REG/FRAME_NUM2_REG).......................................... 13-10 Index Register (INDEX_REG)......................................................................................................... 13-11 END Point0 Control Status Register (EP0_CSR) ............................................................................ 13-12 END Point In Control Status Register (IN_CSR1_REG/IN_CSR2_REG)......................................... 13-14 END Point Out Control Status Register (OUT_CSR1_REG/OUT_CSR2_REG) .............................. 13-16 END Point FIFO Register (EPN_FIFO_REG) ................................................................................. 13-18 MAX Packet Register (MAXP_REG)............................................................................................... 13-19 END Point Out Write Count Register (OUT_FIFO_CNT1_REG/OUT_FIFO_CNT2_REG).............. 13-20 DMA Interface Control Register (EPN_DMA_CON) ........................................................................ 13-21 DMA Unit Counter Register (EPN_DMA_UNIT) .............................................................................. 13-22 DMA FIFO Counter Register (EPN_DMA_FIFO) ............................................................................ 13-23 DMA Total Transfer Counter Register (EPN_DMA_TTC_L,M,H)..................................................... 13-24 S3C2410X MICROPROCESSOR xiii Table of Contents (Continued) Chapter 14 Interrupt Controller Overview ................................................................................................................................................14-1 Interrupt Controller Operation ..........................................................................................................14-2 Interrupt Sources............................................................................................................................14-3 Interrupt Priority Generating Block...................................................................................................14-4 Interrupt Priority..............................................................................................................................14-5 Interrupt Controller Special Registers.......................................................................................................14-6 Source Pending (Srcpnd) Register...................................................................................................14-6 Interrupt Mode (INTMOD) Register..................................................................................................14-8 Interrupt Mask (INTMSK) Register...................................................................................................14-10 Priority Register (PRIORITY)...........................................................................................................14-12 Interrupt Pending (INTPND) Register...............................................................................................14-14 Interrupt Offset (INTOFFSET) Register ...........................................................................................14-16 SUB Source Pending (SUBSRCPND) Register................................................................................14-17 Interrupt Sub Mask (INTSUBMSK) Register ....................................................................................14-18 Chapter 15 LCD Controller Overview ................................................................................................................................................15-1 Features.........................................................................................................................................15-1 Common Features..........................................................................................................................15-2 External Interface Signal .................................................................................................................15-2 Block Diagram................................................................................................................................15-3 STN LCD Controller Operation ................................................................................................................15-4 Timing Generator (TIMEGEN).........................................................................................................15-4 Video Operation ..............................................................................................................................15-5 Dithering and Frame Rate Control ...................................................................................................15-7 Memory Data Format (STN, BSWP=0)............................................................................................15-9 TFT LCD Controller Operation.................................................................................................................15-15 Video Operation ..............................................................................................................................15-15 Memory Data Format (TFT).............................................................................................................15-16 256 Palette Usage (TFT) .................................................................................................................15-20 Samsung TFT LCD Panel (3.5² Portrait / 256k Color /Reflective A-SI TFT LCD) .............................15-23 Virtual Display (TFT/STN) ...............................................................................................................15-24 LCD Power Enable (STN/TFT) ........................................................................................................15-25 LCD Controller Special Registers ....................................................................................................15-26 Frame Buffer Start Address 1 Register ............................................................................................15-32 xiv S3C2410X MICROPROCESSOR Table of Contents (Continued) Chapter 16 A/D Converter Overview ............................................................................................................................................... 16-1 Features ........................................................................................................................................ 16-1 ADC & Touch Screen Interface Operation............................................................................................... 16-2 Block Diagram............................................................................................................................... 16-2 Example for Touch Screen ............................................................................................................. 16-3 Function Descriptions ..................................................................................................................... 16-4 ADC and Touch Screen Interface Special Registers................................................................................ 16-7 ADC Control (ADCCON) Register................................................................................................... 16-7 ADC Touch Screen Control (ADCTSC) Register............................................................................. 16-8 ADC Start Delay (ADCDLY) Register.............................................................................................. 16-9 ADC Conversion Data (ADCDAT1) Register................................................................................... 16-11 Chapter 17 RTC (Real Time Clock) Overview ............................................................................................................................................... 17-1 Features ........................................................................................................................................ 17-1 Real Time Clock Operation............................................................................................................. 17-2 Leap Year Generator ...................................................................................................................... 17-2 Read/Write Registers ..................................................................................................................... 17-3 Backup Battery Operation............................................................................................................... 17-3 Alarm Function ............................................................................................................................... 17-3 Tick Time Interrupt ......................................................................................................................... 17-3 Round Reset Function .................................................................................................................... 17-3 32.768kHz X-Tal Connection Example .......................................................................................... 17-4 Real Time Clock Special Registers ......................................................................................................... 17-5 Real Time Clock Control (RTCCON) Register ................................................................................ 17-5 Tick Time Count (TICNT) Register ................................................................................................. 17-5 RTC Alarm Control (RTCALM) Register ......................................................................................... 17-6 Alarm Second Data (ALMSEC) Register......................................................................................... 17-7 Alarm Min Data (ALMMIN) Register................................................................................................ 17-7 Alarm Hour Data (ALMHOUR) Register.......................................................................................... 17-7 Alarm Date Data (ALMDATE) Register ........................................................................................... 17-8 Alarm Mon Data (ALMMON) Register............................................................................................. 17-8 Alarm Year Data (ALMYEAR) Register........................................................................................... 17-8 RTC Round Reset (RTCRST) Register........................................................................................... 17-9 BCD Second (BCDSEC) Register................................................................................................... 17-9 BCD Minute (BCDMIN) Register..................................................................................................... 17-9 BCD Hour (BCDHOUR) Register .................................................................................................... 17-10 BCD Date (BCDDATE) Register ..................................................................................................... 17-10 BCD Day (BCDDAY) Register ........................................................................................................ 17-10 BCD Month (BCDMON) Register.................................................................................................... 17-11 BCD Year (BCDYEAR) Register ..................................................................................................... 17-11 S3C2410X MICROPROCESSOR xv Table of Contents (Continued) Chapter 18 Watchdog Timer Overview ................................................................................................................................................18-1 Features.........................................................................................................................................18-1 Watchdog Timer Operation .............................................................................................................18-2 WTDAT & WTCNT..........................................................................................................................18-2 Consideration of Debugging Environment........................................................................................18-2 Watchdog Timer Special Registers..........................................................................................................18-3 Watchdog Timer Control (WTCON) Register...................................................................................18-3 Watchdog Timer Data (WTDAT) Register .......................................................................................18-4 Watchdog Timer Count (WTCNT) Register .....................................................................................18-4 Chapter 19 SDI Interface Overview ................................................................................................................................................19-1 Features.........................................................................................................................................19-1 Block Diagram................................................................................................................................19-2 SDI Operation ................................................................................................................................19-3 SDIO Operation..............................................................................................................................19-4 SDI Special Registers......................................................................................................................19-5 Chapter 20 IIC-Bus Interface Overview ................................................................................................................................................20-1 The IIC-Bus Interface ......................................................................................................................20-3 Start and Stop Conditions................................................................................................................20-3 Data Transfer Format ......................................................................................................................20-4 ACK Signal Transmission ................................................................................................................20-5 Read-Write Operation .....................................................................................................................20-6 Bus Arbitration Procedures ..............................................................................................................20-6 Abort Conditions.............................................................................................................................20-6 Configuring the IIC-Bus ...................................................................................................................20-6 Flowcharts of the Operations in Each Mode.....................................................................................20-7 IIC-Bus Interface Special Registers..........................................................................................................20-11 Multi-Master IIC-Bus Control Register (IICCON) ..............................................................................20-11 Multi-Master IIC-Bus Address Register (IICADD) .............................................................................20-13 Multi-Master IIC-Bus Transmit/Receive Data Shift Register (IICDS) ................................................20-13 xvi S3C2410X MICROPROCESSOR Table of Contents (Continued) Chapter 21 IIS-Bus Interface Overview ............................................................................................................................................... 21-1 Block Diagram ....................................................................................................................................... 21-2 Functional Descriptions.......................................................................................................................... 21-2 Transmit or Receive only Mode ...................................................................................................... 21-2 Audio Serial Interface Format ................................................................................................................. 21-3 IIS-Bus Format ............................................................................................................................... 21-3 MSB (Left) Justified ........................................................................................................................ 21-3 Sampling Frequency and Master Clock........................................................................................... 21-4 IIS-Bus Interface Special Registers............................