Stratix IV GX 开发套件原理图
Stratix IV GX 开发套件原理图,PDF格式
S4GX_PCIE_sch.pdf
Stratix IV GX 开发套件出厂恢复程序
Stratix IV GX 开发套件出厂恢复程序
actory_recovery:
This directory contains the restore.sh script
which writes restore_0 and restore_1 factory
flash files to the flash device on the board
In the unlikely event that factory flash gets erased,
please follow instructions as described in
the User's Guide, chapter entitled:
"Restoring the Flash Device with the Factory Settings"
build_factory_source: For advanced users
This directory contains a build_restore.sh script
which generates the restore_0 and restore_1 factory
flash files from files created by various Altera tools.
For more information refer to build_factory_readme.txt
in the build_factory_source directory
software_resources: For advanced users
This directory contains an html web content directory
and boot_code source directory for generating the software boot loader
For more information refer to web_content_readme.txt
in the software_resources directory
Stratix IV GX 开发套件测试例程源文件
Stratix IV GX 开发套件测试例程源文件,包括board_test_system、board_update_portal、max2
Stratix IV GX 开发套件HSMC_loopback_header原理图和PCB源文件
Stratix IV GX 开发套件HSMC_loopback_header原理图和PCB源文件
Stratix IV GX 开发套件HSMC_breakout_header原理图和PCB源文件
Stratix IV GX 开发套件HSMC_breakout_header原理图和PCB源文件,assembly、layout、schematic
Stratix IV GX 开发套件BOM表
S4GX_PCIE_B.xls:
Number 6XX-41284R
Description STRATIX IV GX F1517 FPGA BOARD (6XX-41284R)
Stratix IV GX 开发套件POWER评估工具
Note that this Decoupling spreadsheet and EPE power estimator spreadsheet
is the original version used for the original pre-silicon PCB design. For
updated version please contct Altera applications. This will be updated
in the QII v9.1sp1 release.
Stratix IV GX 开发套件PCB源文件
Stratix IV GX 开发套件PCB源文件,包含加工文件等(s4_pcie_devkit_revb.brd、100-0310901-b1_revb.tgz)
Stratix IV GX 开发套件用户手册
The Altera®
Stratix
®IV GX FPGA Development Kitis a complete design environment
that includes both the hardware and software you need to develop Stratix IV GX
FPGA designs. The PCI-SIG-compliant board and the one-year license for the
Quartus
®
II software provide everything you need to begin developing custom
Stratix IV GXFPGA designs. The following list describes what you can accomplish
with the development kit:
■ Develop and test PCI Express 2.0 designs
■ Develop and test memory subsystems consisting of DDR3 and QDR II+ memories
■ Build designs capable of migrating to Altera’s low-cost HardCopy®
IV ASICs
■ Take advantage of the modular and scalable design by using the high-speed
mezzanine card (HSMC) connectors to interface to over 20 different HSMCs
provided by Altera partners, supporting protocols such as Serial RapidIO
®
,
10 Gigabit Ethernet, SONET, Common PublicRadio Interface (CPRI), Open Base
Station Architecture Initiative (OBSAI) and others
Hardware
■ Stratix IV GX FPGA development board—A development platform that allows
you to develop and prototype hardware designs running on the Stratix IV GX
EP4SGX230 FPGA.
■ For detailed information about the board components and interfaces, refer to the
Stratix IV GX FPGA Development Board Reference Manual.
■ Power supply and cables—The development kit includes the following items:
■ Power supply and AC adapters for North America/Japan, Europe, and the
United Kingdom
■ USB cable
■ Ethernet cable
■ SMB cable
This user guide leads you through the following Stratix IV GXFPGA development
board setup steps:
■ Inspecting the contents of the kit
■ Installing the Altera Complete Design Suite DVD software
■ Setting up, powering up, and verifying correct operation of the development
board
■ Configuring the Stratix IV GX FPGA
■ Running the Board Test System designs
Stratix IV GX 开发套件参考手册
This document describes the hardware features of the Stratix®
IV GX FPGA
development board, including the detailed pin-out and component reference
information required to create custom FPGA designs that interface with all
components of the board.
The Stratix IV GX FPGA development board provides a hardware platform for
developing and prototyping low-power, high-performance, and logic-intensive
designs. The board provides a wide range of peripherals and memory interfaces to
facilitate the development of the Stratix IV GX FPGA designs.
Two High-Speed Mezzanine Card (HSMC) connectors are available to add additional
functionality via a variety of HSMC cards available from both Altera and various
partners
Design advancements and innovations, such as the 8.5 Gbps transceiver modules, the
PCI Express hard IP implementation, and programmable power technology ensure
that designs implemented in the Stratix IV GX FPGAs operate faster, with lower
power than in previous FPGA families.
The board features the following major component blocks:
■ EP4SGX230KF40 FPGA in the 1517-pin FineLine BGA Package
■ 228,000 LEs
■ 91,200 adaptive logic modules (ALMs)
■ 17,133 Kbit on-die memory
■ 126.5 Gbps transceivers (PMA only)
■ 2 PCI Express hard IP blocks
■ 8 phase locked loops (PLLs)
■ 1288 18x18 multipliers
■ 0.9-V core power
■ MAX®
II CPLD EPM2210 System Controller in the 256-pin FineLine BGA Package
■ 1.8-V core power
■ FPGA Configuration Circuitry
■ MAX®
II CPLD EPM2210 System Controller and Flash Fast Passive Parallel
(FPP) configuration
■ On-Board USB-BlasterTM
for use with the Quartus
®
II Programmer
■ On-Board Clocking Circuitry
■ 50-MHz/100-MHz/125-MHz/148.5-MHz/155.52-MHz/156.25-MHz oscillator
■ SMA connectors for external clock input
■ SMA connectors for clock output
■ Memory devices
■ 512-Mbyte DDR3 SDRAM with a 64-bit data bus (bottom port)
■ 128-Mbyte DDR3 SDRAM with a 16-bit data bus (top port)
■ Two 4-Mbyte QDRII+ SRAMs with 18-bit data buses
■ 2-Mbyte SSRAM
Stratix IV GX 开发套件快速上手指南
Altera’s Stratix IV GX FPGA Development Kit,
which comes with a one-year license for the
Quartus II software, provides all that’s needed to
begin development for a variety of serial protocols.
You can use this development kit to:
• Develop and test PCI Express 2.0 designs using the
PCI-SIG-compliant development board
• Develop and test memory subsystems consisting
of DDR3 and QDRII+ memory
• Build designs capable of migrating to Altera’s
low-cost HardCopy® IV ASICs
• Take advantage of the modular and scalable design
by using high-speed mezzanine card (HSMC)
connectors to interface to one of over 20 different
HSMCs provided by Altera partners.
• Available HSMCs support protocols such as
Serial RapidIO®, 10 Gigabit Ethernet, SONET,
CPRI, OBSAI, and many others
SEED-HPS6455板卡平台软件-TMS320C6455-千兆以太网-srio
SEED-HPS6455的主要特点有:
DSP处理器:TMS320C6455BZTZ2,主频1200MHz;
FPGA:XC5VSX50T,封装FFG1136;
64位160MHz的总线连接FPGA与DSP实现高达10Gbit的带宽;
两片105M ADC AD6645(14位),组成2路模拟输入;
一片160M/400M DAC AD9777(16位),支持2路模拟输出;
一片正交调制器AD8345;
低抖动锁相环CDCE62005支持5路LVDS/LVPECL输出;
2路RS232接口,DB9连接器;
FLASH存储器: S29GL128,128Mb,采用8bit模式;
DDR2-667 SDRAM 存储器:4片MT47H64M16-3,共4Gb(最大兼容8Gb);
支持ESAM(SLE66C161PE);
SPI FLASH:AT45DB321D,32Mb,用于存放FPGA的程序;
I2C EEPROM :256Kb AT24C256BN与DSP相连;
PCI 33/66接口;
10/100/1000M自适应网络接口(1G PHY:VSC8641XKO)。
64位EMIF连接FPGA和DSP;
x4 RAPID IO连接FPGA和DSP;
McBSP连接FPGA和DSP;
16路带缓冲差分GPIO;
SMA外部数字输入;
SMA外部时钟输入;
SMA外部中频输入;
JTAG调试接口;
SEED-HPS6455板卡平台器件手册资料-TMS320C6455-千兆以太网-srio
SEED-HPS6455的主要特点有:
DSP处理器:TMS320C6455BZTZ2,主频1200MHz;
FPGA:XC5VSX50T,封装FFG1136;
64位160MHz的总线连接FPGA与DSP实现高达10Gbit的带宽;
两片105M ADC AD6645(14位),组成2路模拟输入;
一片160M/400M DAC AD9777(16位),支持2路模拟输出;
一片正交调制器AD8345;
低抖动锁相环CDCE62005支持5路LVDS/LVPECL输出;
2路RS232接口,DB9连接器;
FLASH存储器: S29GL128,128Mb,采用8bit模式;
DDR2-667 SDRAM 存储器:4片MT47H64M16-3,共4Gb(最大兼容8Gb);
支持ESAM(SLE66C161PE);
SPI FLASH:AT45DB321D,32Mb,用于存放FPGA的程序;
I2C EEPROM :256Kb AT24C256BN与DSP相连;
PCI 33/66接口;
10/100/1000M自适应网络接口(1G PHY:VSC8641XKO)。
64位EMIF连接FPGA和DSP;
x4 RAPID IO连接FPGA和DSP;
McBSP连接FPGA和DSP;
16路带缓冲差分GPIO;
SMA外部数字输入;
SMA外部时钟输入;
SMA外部中频输入;
JTAG调试接口;
SEED-HPS6455板卡平台用户测试测试例程-TMS320C6455-千兆以太网-srio
SEED-HPS6455的主要特点有:
DSP处理器:TMS320C6455BZTZ2,主频1200MHz;
FPGA:XC5VSX50T,封装FFG1136;
64位160MHz的总线连接FPGA与DSP实现高达10Gbit的带宽;
两片105M ADC AD6645(14位),组成2路模拟输入;
一片160M/400M DAC AD9777(16位),支持2路模拟输出;
一片正交调制器AD8345;
低抖动锁相环CDCE62005支持5路LVDS/LVPECL输出;
2路RS232接口,DB9连接器;
FLASH存储器: S29GL128,128Mb,采用8bit模式;
DDR2-667 SDRAM 存储器:4片MT47H64M16-3,共4Gb(最大兼容8Gb);
支持ESAM(SLE66C161PE);
SPI FLASH:AT45DB321D,32Mb,用于存放FPGA的程序;
I2C EEPROM :256Kb AT24C256BN与DSP相连;
PCI 33/66接口;
10/100/1000M自适应网络接口(1G PHY:VSC8641XKO)。
64位EMIF连接FPGA和DSP;
x4 RAPID IO连接FPGA和DSP;
McBSP连接FPGA和DSP;
16路带缓冲差分GPIO;
SMA外部数字输入;
SMA外部时钟输入;
SMA外部中频输入;
JTAG调试接口;
测试代码:
FPGA与PC的UART通信
FPGA控制LED
FPGA DDR2控制器测试
ADC/DAC PLL测试
DSP 控制LED
DSP DDR2控制器测试
DSP MAC控制Gbit PHY
实时FFT
PCI接口测试
SEED-HPS6455板卡平台用户指南-TMS320C6455-千兆以太网-srio
SEED-HPS6455作为一款高性能数字信号处理平台,为您提供了丰富的运算资源和高
速接口资源,以适应雷达信号处理、卫星通信系统、软件无线电、高速宽带数据传输等应用
对大数据量信号处理实时性、精度以及高速传输的苛刻要求。同时,HPS6455还可以作为
一款DSP+FPGA的参考设计,完备的硬件原理图和例程为您的设计提供了可靠的参考,缩
短您产品的上市时间。
SEED-HPS6455的主要特点有:
DSP处理器:TMS320C6455BZTZ2,主频1200MHz;
FPGA:XC5VSX50T,封装FFG1136;
64位160MHz的总线连接FPGA与DSP实现高达10Gbit的带宽;
两片105M ADC AD6645(14位),组成2路模拟输入;
一片160M/400M DAC AD9777(16位),支持2路模拟输出;
一片正交调制器AD8345;
低抖动锁相环CDCE62005支持5路LVDS/LVPECL输出;
2路RS232接口,DB9连接器;
FLASH存储器: S29GL128,128Mb,采用8bit模式;
DDR2-667 SDRAM 存储器:4片MT47H64M16-3,共4Gb(最大兼容8Gb);
支持ESAM(SLE66C161PE);
SPI FLASH:AT45DB321D,32Mb,用于存放FPGA的程序;
I2C EEPROM :256Kb AT24C256BN与DSP相连;
PCI 33/66接口;
10/100/1000M自适应网络接口(1G PHY:VSC8641XKO)。
64位EMIF连接FPGA和DSP;
x4 RAPID IO连接FPGA和DSP;
McBSP连接FPGA和DSP;
16路带缓冲差分GPIO;
SMA外部数字输入;
SMA外部时钟输入;
SMA外部中频输入;
JTAG调试接口;
SEED-HPS6455板卡平台的原理图-TMS320C6455-千兆以太网口-srio
SEED-HPS6455作为一款高性能数字信号处理平台,为您提供了丰富的运算资源和高
速接口资源,以适应雷达信号处理、卫星通信系统、软件无线电、高速宽带数据传输等应用
对大数据量信号处理实时性、精度以及高速传输的苛刻要求。同时,HPS6455还可以作为
一款DSP+FPGA的参考设计,完备的硬件原理图和例程为您的设计提供了可靠的参考,缩
短您产品的上市时间。
SEED-HPS6455的主要特点有:
DSP处理器:TMS320C6455BZTZ2,主频1200MHz;
FPGA:XC5VSX50T,封装FFG1136;
64位160MHz的总线连接FPGA与DSP实现高达10Gbit的带宽;
两片105M ADC AD6645(14位),组成2路模拟输入;
一片160M/400M DAC AD9777(16位),支持2路模拟输出;
一片正交调制器AD8345;
低抖动锁相环CDCE62005支持5路LVDS/LVPECL输出;
2路RS232接口,DB9连接器;
FLASH存储器: S29GL128,128Mb,采用8bit模式;
DDR2-667 SDRAM 存储器:4片MT47H64M16-3,共4Gb(最大兼容8Gb);
支持ESAM(SLE66C161PE);
SPI FLASH:AT45DB321D,32Mb,用于存放FPGA的程序;
I2C EEPROM :256Kb AT24C256BN与DSP相连;
PCI 33/66接口;
10/100/1000M自适应网络接口(1G PHY:VSC8641XKO)。
64位EMIF连接FPGA和DSP;
x4 RAPID IO连接FPGA和DSP;
McBSP连接FPGA和DSP;
16路带缓冲差分GPIO;
SMA外部数字输入
SMA外部时钟输入
SMA外部中频输入
JTAG调试接口;
TDS510驱动.rar
TDS510USB仿真器适用于工作电压在1.0到5.0伏之间的TMS320
系列数字信号处理器。仿真器为USB2.0接口设备,支持即插即用
及热插拔。支持windows98/2000/XP。
1. 支持TI的C2000、VC33、C5000、C6000系列芯片。
2. 支持1.0~5.0伏目标DSP电压。
3. 采用USB2.0接口,传输速度可达到480Mb/s,完全即插即用,
无跳线。
4. 兼容USB1.1接口,可直接插在USB1.1接口上使用,在USB1.1
接口上传输速度为12Mb/s。
5. 支持热插拔,TDS510USB仿真器可以在不关闭主机的情况下插
拔而不会损坏。
6. 通过USB接口供电,无需外接电源。
7. 支持Texas Instrument的Code Composer Studio(CCS)。
XDS560二代.rar
XDS560V2是目前的XDS510和XDS560系列仿真器的下一代产品,
在旧产品的基础上增加了控制及采集跟踪/回溯(Trace)数据的功能。
XDS560v2 DTC 支持:
z 控制IEEE1149.1 JTAG兼容TAP(Test Access Port)
z 调试IEEE1149.1兼容接口
z 调试IEEE1149.7兼容接口
z 通过1-4针的Trace口采集跟踪/回溯数据
z 通过USB或网口与主机进行通讯
硬件参数:
z TMS320DM6441 (405/513 MHz)
z 256 MBytes of DDR2 SDRAM
z 64 MBytes of NAND flash
z 10/100 ENET
z USB 2.0
z Samtec connector interface, 25x2 (QSS-025-RA)
z Samtec SQCD-025-12.00-STR-TEU-1-S cable
z MIPI -60 buffered emulation/trace connector
z MIPI60 to CTI 20 pin adapter
z 5V input power with LED
z 16-bit EMIF DM6441 interface to FPGA
z 16-bit Video interface from FPGA to DM6441
z Cyclone III FPGA
z 6 Status LEDs
z Boot-mode jumper
支持功能:
z IEEE 1149.1 调试
z IEEE 1149.7 调试
z 通过EMU管脚控制Boot mode
z 系统跟踪/回溯(System Trace)
BCM5396 BCM5389 BCM5387设计手册
BCM5396 and BCM5389/BCM5387 Design Guidelines,
文档编号:538X_5396-AN105-R。538X_5396-AN102-R 04/24/06 Updated。文档页数68页。千兆以太网交换芯片的设计手册,硬件设计必备。
BCM5396 Data Sheet
BCM5396数据手册,编号:5396-DS113-R,文档日期:February 07, 2012
5396-DS113-R 02/07/12 Updated。文档页数:195页。
BCM5396是一款千兆以太网交换芯片。
VSC8641器件手册-datasheet
VSC8641官方器件手册,Vitesse 公司 10/100/1000M以太网PHY