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EDA十进制频率计数器
VHDL语言写的十进制频率计数器
==============================
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity cnt10 is
port (rst,clk,ena:in std_logic;
cout: out std_logic;
outy :out std_logic_vector(3 downto 0));
end cnt10;
architecture behv of cnt10 is
begin
process (rst,ena,clk)
variable cqi :std_logic_vector(3 downto 0);
begin
if rst='1' then cqi :=(others =>'0');
elsif clk'event and clk='1' then
if ena ='1' then
if cqi < 9 then cqi:=cqi+1;cout<='0';
elsif cqi=9 then
cqi :=(others =>'0');
cout<='1';
end if;
elsif ena='0' then cqi:=(others =>'0');
end if;
end if;
outy <=cqi;
end process;
end behv;
2011-11-22
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