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library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity mod2 is port(clk,rst,m,en:in std_logic; cq1:out std_logic_vector(3 downto 0); cq2:out std_logic_vector(3 downto 0)); end mod2; architecture behav of mod2 is signal cql:std_logic_vector(3 downto 0); signal cqh:std_logic_vector(3 downto 0); begin cq2<=cqh; cq1<=cql; process(rst,clk,m) begin if rst='1' then cql<="0000";cqh<="0000"; elsif clk'event and clk='1' then if en='1' then case m is when '0' =>if cql=9 then cql<="0000";cqh<=cqh+1; else cql<=cql+1; end if; if cqh=2 and cql=2 then cqh<="0000";cql<="0000"; end if; if cqh>1 and cql>2 then cqh<="0000";cql<="0000"; end if; when '1' =>if cql=9 then cql<="0000";cqh<=cqh+1; else cql<=cql+1; end if; if cqh=6 and cql=6 then cqh<="0000";cql<="0000"; end if; end case; end if; end if; end process; end behav;

library ieee; use ieee.std_logic_1164.all; entity addt is port (ain,bin,cin :in std_logic; cout,sum :out std_logic); end entity addt; architecture fd1 of addt is component h_adder port(a,b: in std_logic; co,so:out std_logic); end component; component or2a port(a,b:in std_logic; c:out std_logic); end component; signal d,e,f :std_logic; begin u1:h_adder port map(a=>ain,b=>bin,co=>d,so=>e); u2:h_adder port map(a=>e,b=>cin,co=>f,so=>sum); u3:or2a port map(a=>d,b=>f,c=>cout); end architecture fd1;

LIBRARY ieee; USE ieee.std_logic_1164.all; LIBRARY lpm; USE lpm.all; ENTITY lrc IS PORT ( address : IN STD_LOGIC_VECTOR (7 DOWNTO 0); inclock : IN STD_LOGIC ; outclock : IN STD_LOGIC ; q : OUT STD_LOGIC_VECTOR (3 DOWNTO 0) ); END lrc; ARCHITECTURE SYN OF lrc IS SIGNAL sub_wire0 : STD_LOGIC_VECTOR (3 DOWNTO 0); COMPONENT lpm_rom GENERIC ( intended_device_family : STRING; lpm_address_control : STRING; lpm_file : STRING; lpm_outdata : STRING; lpm_type : STRING; lpm_width : NATURAL; lpm_widthad : NATURAL ); PORT ( outclock : IN STD_LOGIC ; address : IN STD_LOGIC_VECTOR (7 DOWNTO 0); inclock : IN STD_LOGIC ; q : OUT STD_LOGIC_VECTOR (3 DOWNTO 0) ); END COMPONENT; BEGIN q <= sub_wire0(3 DOWNTO 0); lpm_rom_component : lpm_rom GENERIC MAP ( intended_device_family => "ACEX1K", lpm_address_control => "REGISTERED", lpm_file => "music.hex", lpm_outdata => "REGISTERED", lpm_type => "LPM_ROM", lpm_width => 4, lpm_widthad => 8 ) PORT MAP ( outclock => outclock, address => address, inclock => inclock, q => sub_wire0 ); END SYN;