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To design a chip,one needs to come up with the Specifications first, The next step is in the flow is to come up with the Structural and Functional Description.Once Functional Verification is completed, the RTL is converted into an optimized Gate Level Netlist. This step is called Logic/RTL synthesis.The next step in the ASIC flow is the Physical Implementation of the Gate Level Netlist.

a FTL for ssd need to be distributed on on chip sram or off chip dram